Patchwork [v2,11/14] target-arm: Move cache ID register setup to cpu specific init fns

login
register
mail settings
Submitter Peter Maydell
Date April 14, 2012, 4:42 p.m.
Message ID <1334421743-31146-13-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/152526/
State New
Headers show

Comments

Peter Maydell - April 14, 2012, 4:42 p.m.
Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu-qom.h |    5 +++++
 target-arm/cpu.c     |   11 +++++++++++
 target-arm/helper.c  |   13 ++-----------
 3 files changed, 18 insertions(+), 11 deletions(-)
Andreas Färber - April 20, 2012, 4 p.m.
Am 14.04.2012 18:42, schrieb Peter Maydell:
> Move cache ID register reset out of cpu_reset_model_id() by
> creating a field for the reset value in ARMCPU and setting it
> up in the cpu specific init functions.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/cpu-qom.h |    5 +++++
>  target-arm/cpu.c     |   11 +++++++++++
>  target-arm/helper.c  |   13 ++-----------
>  3 files changed, 18 insertions(+), 11 deletions(-)
[...]
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 924aaed..63de462 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -269,6 +269,10 @@ static void cortex_a8_initfn(Object *obj)
>      cpu->id_isar2 = 0x21232031;
>      cpu->id_isar3 = 0x11112131;
>      cpu->id_isar4 = 0x00111142;
> +    cpu->clidr = (1 << 27) | (2 << 24) | 3;
> +    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
> +    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
> +    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
>  }
>  
>  static void cortex_a9_initfn(Object *obj)
> @@ -302,6 +306,9 @@ static void cortex_a9_initfn(Object *obj)
>      cpu->id_isar2 = 0x21232041;
>      cpu->id_isar3 = 0x11112131;
>      cpu->id_isar4 = 0x00111142;
> +    cpu->clidr = (1 << 27) | (2 << 24) | 3;

Copy&paste, should be (1 << 27) | (1 << 24) | 3.

/-F

> +    cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
> +    cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
>  }
>  
>  static void cortex_a15_initfn(Object *obj)
[...]
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index fb618a7..5cbc7e0 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -25,21 +25,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
>      case ARM_CPUID_ARM11MPCORE:
>          break;
>      case ARM_CPUID_CORTEXA8:
> -        env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
> -        env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
> -        env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
> -        env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
>          break;
>      case ARM_CPUID_CORTEXA9:
> -        env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
> -        env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
> -        env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
>          break;
>      case ARM_CPUID_CORTEXA15:
> -        env->cp15.c0_clid = 0x0a200023;
> -        env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
> -        env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
> -        env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
>          break;
>      case ARM_CPUID_CORTEXM3:
>          break;
[snip]
Peter Maydell - April 20, 2012, 4:05 p.m.
On 20 April 2012 17:00, Andreas Färber <afaerber@suse.de> wrote:
> Am 14.04.2012 18:42, schrieb Peter Maydell:
>> +    cpu->clidr = (1 << 27) | (2 << 24) | 3;
>
> Copy&paste, should be (1 << 27) | (1 << 24) | 3.

Fixed and pushed, sigh.

-- PMM
Andreas Färber - April 20, 2012, 4:31 p.m.
Am 20.04.2012 18:05, schrieb Peter Maydell:
> On 20 April 2012 17:00, Andreas Färber <afaerber@suse.de> wrote:
>> Am 14.04.2012 18:42, schrieb Peter Maydell:
>>> +    cpu->clidr = (1 << 27) | (2 << 24) | 3;
>>
>> Copy&paste, should be (1 << 27) | (1 << 24) | 3.
> 
> Fixed and pushed, sigh.

Acked-by: Andreas Färber <afaerber@suse.de>

/-F

Patch

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 7603eff..b6c044a 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -89,6 +89,11 @@  typedef struct ARMCPU {
     uint32_t id_isar3;
     uint32_t id_isar4;
     uint32_t id_isar5;
+    uint32_t clidr;
+    /* The elements of this array are the CCSIDR values for each cache,
+     * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
+     */
+    uint32_t ccsidr[16];
 } ARMCPU;
 
 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 924aaed..63de462 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -269,6 +269,10 @@  static void cortex_a8_initfn(Object *obj)
     cpu->id_isar2 = 0x21232031;
     cpu->id_isar3 = 0x11112131;
     cpu->id_isar4 = 0x00111142;
+    cpu->clidr = (1 << 27) | (2 << 24) | 3;
+    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
+    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
+    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 }
 
 static void cortex_a9_initfn(Object *obj)
@@ -302,6 +306,9 @@  static void cortex_a9_initfn(Object *obj)
     cpu->id_isar2 = 0x21232041;
     cpu->id_isar3 = 0x11112131;
     cpu->id_isar4 = 0x00111142;
+    cpu->clidr = (1 << 27) | (2 << 24) | 3;
+    cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
+    cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 }
 
 static void cortex_a15_initfn(Object *obj)
@@ -333,6 +340,10 @@  static void cortex_a15_initfn(Object *obj)
     cpu->id_isar2 = 0x21232041;
     cpu->id_isar3 = 0x11112131;
     cpu->id_isar4 = 0x10011142;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 }
 
 static void ti925t_initfn(Object *obj)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fb618a7..5cbc7e0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -25,21 +25,10 @@  static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     case ARM_CPUID_ARM11MPCORE:
         break;
     case ARM_CPUID_CORTEXA8:
-        env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
-        env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
-        env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
-        env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
         break;
     case ARM_CPUID_CORTEXA9:
-        env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
-        env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
-        env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
         break;
     case ARM_CPUID_CORTEXA15:
-        env->cp15.c0_clid = 0x0a200023;
-        env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
-        env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
-        env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
         break;
     case ARM_CPUID_CORTEXM3:
         break;
@@ -113,6 +102,8 @@  void cpu_state_reset(CPUARMState *env)
     env->cp15.c0_c2[4] = cpu->id_isar4;
     env->cp15.c0_c2[5] = cpu->id_isar5;
     env->cp15.c15_i_min = 0xff0;
+    env->cp15.c0_clid = cpu->clidr;
+    memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
 
     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';