From patchwork Fri Apr 13 08:00:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Behme Dirk (CM/ESO2)" X-Patchwork-Id: 152259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4702EB6FDB for ; Fri, 13 Apr 2012 18:00:57 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3718C28083; Fri, 13 Apr 2012 10:00:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HAlTi3iW+J0e; Fri, 13 Apr 2012 10:00:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 69D1B2807B; Fri, 13 Apr 2012 10:00:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 88D172807B for ; Fri, 13 Apr 2012 10:00:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LEVyoSaRzZg9 for ; Fri, 13 Apr 2012 10:00:38 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp2-v.fe.bosch.de (smtp2-v.fe.bosch.de [139.15.237.6]) by theia.denx.de (Postfix) with ESMTPS id 72B4428078 for ; Fri, 13 Apr 2012 10:00:33 +0200 (CEST) Received: from vsmta11.fe.internet.bosch.com (unknown [10.4.98.30]) by imta24.fe.bosch.de (Postfix) with ESMTP id BA86BB00213 for ; Fri, 13 Apr 2012 10:00:32 +0200 (CEST) Received: from localhost (vsgw4.fe.internet.bosch.com [10.4.98.12]) by vsmta11.fe.internet.bosch.com (Postfix) with SMTP id 924C543C0716 for ; Fri, 13 Apr 2012 10:00:32 +0200 (CEST) Received: from SI-MBX1000.de.bosch.com (10.3.144.121) by fe-hub04.de.bosch.com (10.3.153.63) with Microsoft SMTP Server (TLS) id 8.3.245.1; Fri, 13 Apr 2012 10:00:32 +0200 Received: from SI-HUB1000.de.bosch.com (10.4.103.106) by SI-MBX1000.de.bosch.com (10.3.144.121) with Microsoft SMTP Server (TLS) id 14.2.283.3; Fri, 13 Apr 2012 10:00:31 +0200 Received: from hi-z5661.hi.de.bosch.com (10.34.219.178) by SI-HUB1000.de.bosch.com (10.4.103.106) with Microsoft SMTP Server id 14.2.283.3; Fri, 13 Apr 2012 10:00:29 +0200 Received: from localhost.localdomain (localhost [127.0.0.1]) by hi-z5661.hi.de.bosch.com (Postfix) with ESMTP id 671EC426D2; Fri, 13 Apr 2012 10:00:29 +0200 (CEST) From: Dirk Behme To: Date: Fri, 13 Apr 2012 10:00:28 +0200 Message-ID: <1334304028-25575-1-git-send-email-dirk.behme@de.bosch.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 Cc: Dirk Behme , Jason Chen , Ranjani Vaidyanathan Subject: [U-Boot] [PATCH] i.MX6: Add ANATOP regulator init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter. Note: This should be but can't be done in the DCD. The bootloader prevents access to the ANATOP registers. Signed-off-by: Dirk Behme CC: Jason Chen CC: Jason Liu CC: Ranjani Vaidyanathan CC: Stefano Babic CC: Fabio Estevam Acked-by:Jason Liu --- arch/arm/cpu/armv7/mx6/soc.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 543b2cc..957ea34 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -77,10 +77,26 @@ void init_aips(void) writel(0x00000000, &aips2->opacr4); } +static void init_anatop_reg(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg = readl(&anatop->reg_core); + + /* + * Increase the VDDSOC to 1.2V + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) + * and set them to 1.2V (0.7V + 0x14 * 0.025V) + */ + reg = (reg & ~(0x1F << 18)) | (0x14 << 18); + writel(reg, &anatop->reg_core); +} + int arch_cpu_init(void) { init_aips(); + init_anatop_reg(); + return 0; } #endif