From patchwork Fri Apr 6 13:25:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 151186 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 89461B7097 for ; Fri, 6 Apr 2012 23:28:45 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D964280AC; Fri, 6 Apr 2012 15:28:43 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tl+HvqLrgSqF; Fri, 6 Apr 2012 15:28:43 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 96E8A280A0; Fri, 6 Apr 2012 15:28:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 154AB280A0 for ; Fri, 6 Apr 2012 15:28:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1Xi-3oPTUugv for ; Fri, 6 Apr 2012 15:28:35 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTPS id 1F7782809E for ; Fri, 6 Apr 2012 15:28:33 +0200 (CEST) Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3VPMDd0S68z3hhwW; Fri, 6 Apr 2012 15:28:33 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.8.164]) by mail.m-online.net (Postfix) with ESMTP id 3VPMDd2CDxz4KK7K; Fri, 6 Apr 2012 15:28:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from smtp-auth.mnet-online.de ([192.168.8.180]) by localhost (dynscan1.mail.m-online.net [192.168.8.164]) (amavisd-new, port 10024) with ESMTP id w8CIQyyXyRNi; Fri, 6 Apr 2012 15:28:29 +0200 (CEST) Received: from mashiro.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA; Fri, 6 Apr 2012 15:28:29 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Fri, 6 Apr 2012 15:25:07 +0200 Message-Id: <1333718707-6443-2-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.7.9.1 In-Reply-To: <1333718707-6443-1-git-send-email-marex@denx.de> References: <1333718707-6443-1-git-send-email-marex@denx.de> Cc: Marek Vasut Subject: [U-Boot] [PATCH 2/2] ARM926EJS: Fix cache.c to comply with checkpatch.pl X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Albert ARIBAUD --- arch/arm/cpu/arm926ejs/cache.c | 17 ++++++++--------- 1 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 0b36294..1d3dc6e 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -30,7 +30,7 @@ void invalidate_dcache_all(void) { - asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); } void flush_dcache_all(void) @@ -40,7 +40,7 @@ void flush_dcache_all(void) "mrc p15, 0, r15, c7, c14, 3\n" "bne 0b\n" "mcr p15, 0, %0, c7, c10, 4\n" - ::"r"(0):"memory" + : : "r"(0) : "memory" ); } @@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; } } @@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop) return; while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; } - asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); } void flush_cache(unsigned long start, unsigned long size) @@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size) /* * Stub implementations for l2 cache operations */ -void __l2_cache_disable(void) -{ -} +void __l2_cache_disable(void) {} + void l2_cache_disable(void) - __attribute__((weak, alias("__l2_cache_disable"))); + __attribute__((weak, alias("__l2_cache_disable")));