Patchwork [SH] Fold big/little endian word code with MSW and LSW

login
register
mail settings
Submitter Oleg Endo
Date April 5, 2012, 6:31 p.m.
Message ID <1333650673.19154.34.camel@yam-132-YW-E178-FTW>
Download mbox | patch
Permalink /patch/151001/
State New
Headers show

Comments

Oleg Endo - April 5, 2012, 6:31 p.m.
Hi,

The attached patch folds some of the code that needs to access high/low
subwords depending on the target endianess by utilizing the existing MSW
and LSW macros.

Tested against rev 185893 with...
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a-single/-mb,
-m4-single/-ml,-m4-single/-mb,
-m4a-single/-ml,-m4a-single/-mb}"

...and no new failures.

OK?

Cheers,
Oleg


ChangeLog:

	* config/sh/sh.c (MSW, LSW): Move macros to...
	* config/sh/sh.h: ...here.
	* config/sh/sh.md: Use MSW and LSW macros where applicable.
Kaz Kojima - April 5, 2012, 10:38 p.m.
Oleg Endo <oleg.endo@t-online.de> wrote:
> The attached patch folds some of the code that needs to access high/low
> subwords depending on the target endianess by utilizing the existing MSW
> and LSW macros.
[snip]
> 	* config/sh/sh.c (MSW, LSW): Move macros to...
> 	* config/sh/sh.h: ...here.
> 	* config/sh/sh.md: Use MSW and LSW macros where applicable.

Exposing three-letter macro MSW and LSW globally looks not
a good idea to me.

Regards,
	kaz
Oleg Endo - April 6, 2012, 12:35 a.m.
On Fri, 2012-04-06 at 07:38 +0900, Kaz Kojima wrote:
> Oleg Endo <oleg.endo@t-online.de> wrote:
> > The attached patch folds some of the code that needs to access high/low
> > subwords depending on the target endianess by utilizing the existing MSW
> > and LSW macros.
> [snip]
> > 	* config/sh/sh.c (MSW, LSW): Move macros to...
> > 	* config/sh/sh.h: ...here.
> > 	* config/sh/sh.md: Use MSW and LSW macros where applicable.
> 
> Exposing three-letter macro MSW and LSW globally looks not
> a good idea to me.

Would 'HIGH_WORD' and 'LOW_WORD' be OK as an alternative?

Cheers,
Oleg
Kaz Kojima - April 6, 2012, 1:46 a.m.
From: Oleg Endo <oleg.endo@t-online.de>
>> Exposing three-letter macro MSW and LSW globally looks not
>> a good idea to me.
> 
> Would 'HIGH_WORD' and 'LOW_WORD' be OK as an alternative?

Sounds better but still a bit too generic.  SH_{HIGH,LOW}_WORD
would be Ok, though not so cool. 

Regards,
	kaz
Oleg Endo - April 6, 2012, 9:53 p.m.
On Fri, 2012-04-06 at 10:46 +0900, Kaz Kojima wrote:
> From: Oleg Endo <oleg.endo@t-online.de>
> >> Exposing three-letter macro MSW and LSW globally looks not
> >> a good idea to me.
> > 
> > Would 'HIGH_WORD' and 'LOW_WORD' be OK as an alternative?
> 
> Sounds better but still a bit too generic.  SH_{HIGH,LOW}_WORD
> would be Ok, though not so cool. 
> 

On a second thought, it might be better to simplify those cases in
the .md file, where low/high subregs are used by using 'gen_highpart'
and 'gen_lowpart' for example, instead of checking the endianness over
and over again.
I'm trying out a couple of things...

Cheers,
Oleg

Patch

Index: gcc/config/sh/sh.c
===================================================================
--- gcc/config/sh/sh.c	(revision 185894)
+++ gcc/config/sh/sh.c	(working copy)
@@ -61,9 +61,6 @@ 
 
 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
 
-#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
-#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
-
 /* These are some macros to abstract register modes.  */
 #define CONST_OK_FOR_ADD(size) \
   (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
Index: gcc/config/sh/sh.h
===================================================================
--- gcc/config/sh/sh.h	(revision 185893)
+++ gcc/config/sh/sh.h	(working copy)
@@ -483,6 +483,10 @@ 
    numbered.  */
 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
 
+/* Most/least significant (sub)word indices.  */
+#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
+#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
+
 #define MAX_BITS_PER_WORD 64
 
 /* Width in bits of an `int'.  We want just 32-bits, even if words are
Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 185893)
+++ gcc/config/sh/sh.md	(working copy)
@@ -940,15 +940,11 @@ 
    (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
    (match_dup 6)]
 {
-  operands[2]
-    = gen_rtx_REG (SImode,
-		   true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  operands[3]
-    = (operands[1] == const0_rtx
-       ? const0_rtx
-       : gen_rtx_REG (SImode,
-		      true_regnum (operands[1])
-		      + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
+  operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]) + MSW);
+  operands[3] = (operands[1] == const0_rtx
+		 ? const0_rtx
+		 : gen_rtx_REG (SImode, true_regnum (operands[1]) + MSW));
+
   operands[4] = gen_lowpart (SImode, operands[0]);
   operands[5] = gen_lowpart (SImode, operands[1]);
   operands[6] = gen_label_rtx ();
@@ -1452,12 +1448,8 @@ 
   [(const_int 0)]
 {
   rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
-  high0 = gen_rtx_REG (SImode,
-		       true_regnum (operands[0])
-		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  high2 = gen_rtx_REG (SImode,
-		       true_regnum (operands[2])
-		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
+  high0 = gen_rtx_REG (SImode, true_regnum (operands[0]) + MSW);
+  high2 = gen_rtx_REG (SImode, true_regnum (operands[2]) + MSW);
   emit_insn (gen_clrt ());
   emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
   emit_insn (gen_addc1 (high0, high0, high2));
@@ -1580,12 +1572,8 @@ 
   [(const_int 0)]
 {
   rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
-  high0 = gen_rtx_REG (SImode,
-		       true_regnum (operands[0])
-		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  high2 = gen_rtx_REG (SImode,
-		       true_regnum (operands[2])
-		       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
+  high0 = gen_rtx_REG (SImode, true_regnum (operands[0]) + MSW);
+  high2 = gen_rtx_REG (SImode, true_regnum (operands[2]) + MSW);
   emit_insn (gen_clrt ());
   emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
   emit_insn (gen_subc1 (high0, high0, high2));
@@ -3919,13 +3907,11 @@ 
                    (match_operand:DI 2 "const_int_operand" "n")))]
   "TARGET_SH1 && INTVAL (operands[2]) < 32"
 {
-  int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
-  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
-  rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
-  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+  rtx low_src = operand_subword (operands[1], LSW, 0, DImode);
+  rtx high_src = operand_subword (operands[1], MSW, 0, DImode);
   rtx dst = gen_reg_rtx (DImode);
-  rtx low_dst = operand_subword (dst, low_word, 1, DImode);
-  rtx high_dst = operand_subword (dst, high_word, 1, DImode);
+  rtx low_dst = operand_subword (dst, LSW, 1, DImode);
+  rtx high_dst = operand_subword (dst, MSW, 1, DImode);
   rtx tmp0, tmp1;
 
   tmp0 = gen_reg_rtx (SImode);
@@ -4373,15 +4359,12 @@ 
   "TARGET_SH1"
   [(const_int 0)]
 {
-  int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
-  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
+  rtx low_src = operand_subword (operands[1], LSW, 0, DImode);
+  rtx high_src = operand_subword (operands[1], MSW, 0, DImode);
 
-  rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
-  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+  rtx low_dst = operand_subword (operands[0], LSW, 1, DImode);
+  rtx high_dst = operand_subword (operands[0], MSW, 1, DImode);
 
-  rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
-  rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
-
   emit_insn (gen_clrt ());
   emit_insn (gen_negc (low_dst, low_src));
   emit_insn (gen_negc (high_dst, high_src));
@@ -4493,8 +4476,7 @@ 
   "&& reload_completed"
   [(const_int 0)]
 {
-  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
-  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+  rtx high_src = operand_subword (operands[1], MSW, 0, DImode);
   emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
   emit_insn (gen_negdi_cond (operands[0], operands[1], operands[1],
 			     const1_rtx));
@@ -4509,8 +4491,7 @@ 
   "&& reload_completed"
   [(const_int 0)]
 {
-  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
-  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+  rtx high_src = operand_subword (operands[1], MSW, 0, DImode);
 
   emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
   emit_insn (gen_negdi_cond (operands[0], operands[1], operands[1],
@@ -4529,15 +4510,12 @@ 
   "TARGET_SH1"
   [(const_int 0)]
 {
-  int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
-  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
+  rtx low_src = operand_subword (operands[1], LSW, 0, DImode);
+  rtx high_src = operand_subword (operands[1], MSW, 0, DImode);
 
-  rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
-  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+  rtx low_dst = operand_subword (operands[0], LSW, 1, DImode);
+  rtx high_dst = operand_subword (operands[0], MSW, 1, DImode);
 
-  rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
-  rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
-
   rtx skip_neg_label = gen_label_rtx ();
 
   emit_insn (gen_movsi (low_dst, low_src));
@@ -6305,12 +6283,10 @@ 
   rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
   rtx mem2
     = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
-  insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
-					   regno + !! TARGET_LITTLE_ENDIAN),
+  insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, regno + LSW),
 				  mem2, operands[2]));
   add_reg_note (insn, REG_INC, operands[1]);
-  insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
-					       regno + ! TARGET_LITTLE_ENDIAN),
+  insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, regno + MSW),
 				  change_address (mem, SFmode, NULL_RTX),
 				  operands[2]));
   DONE;
@@ -6328,8 +6304,8 @@ 
   int regno = true_regnum (operands[0]);
   rtx addr, insn;
   rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
-  rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
+  rtx reg0 = gen_rtx_REG (SFmode, regno + MSW);
+  rtx reg1 = gen_rtx_REG (SFmode, regno + LSW);
 
   operands[1] = copy_rtx (mem2);
   addr = XEXP (mem2, 0);
@@ -6393,8 +6369,8 @@ 
 {
   int regno = true_regnum (operands[1]);
   rtx insn, addr;
-  rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
+  rtx reg0 = gen_rtx_REG (SFmode, regno + MSW);
+  rtx reg1 = gen_rtx_REG (SFmode, regno + LSW);
 
   operands[0] = copy_rtx (operands[0]);
   PUT_MODE (operands[0], SFmode);
@@ -10117,14 +10093,11 @@ 
   "TARGET_SHMEDIA_FPU && reload_completed"
   [(set (match_dup 5) (match_dup 6))]
 {
-  int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
-  rtx op1 = gen_rtx_REG (SFmode,
-			 (true_regnum (operands[1])
-			  + (INTVAL (operands[4]) ^ endian)));
+  rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1])
+				 + (INTVAL (operands[4]) ^ LSW));
 
-  operands[7] = gen_rtx_REG (SFmode,
-			     (true_regnum (operands[0])
-			      + (INTVAL (operands[3]) ^ endian)));
+  operands[7] = gen_rtx_REG (SFmode, true_regnum (operands[0])
+				     + (INTVAL (operands[3]) ^ LSW));
   operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
 }
   [(set_attr "type" "fparith_media")])
@@ -10145,14 +10118,12 @@ 
   "&& reload_completed"
   [(set (match_dup 4) (match_dup 5))]
 {
-  int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
   rtx op1 = gen_rtx_REG (SFmode,
-			 true_regnum (operands[1]) + endian);
+			 true_regnum (operands[1]) + LSW);
   rtx op2 = gen_rtx_REG (SFmode,
-			 true_regnum (operands[2]) + endian);
+			 true_regnum (operands[2]) + LSW);
 
-  operands[4] = gen_rtx_REG (SFmode,
-			     true_regnum (operands[0]) + endian);
+  operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + LSW);
   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
 }
   [(set_attr "type" "fparith_media")])
@@ -10173,11 +10144,10 @@ 
   "&& reload_completed"
   [(set (match_dup 4) (match_dup 5))]
 {
-  int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
-  rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian));
-  rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian));
+  rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + MSW);
+  rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + MSW);
 
-  operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian));
+  operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + MSW);
   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
 }
   [(set_attr "type" "fparith_media")])