From patchwork Thu Apr 5 15:46:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohammed Afzal X-Patchwork-Id: 150978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 70E3DB7061 for ; Fri, 6 Apr 2012 02:06:28 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SFpBb-000740-0h; Thu, 05 Apr 2012 16:05:23 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SFpAf-0006Ig-Lw; Thu, 05 Apr 2012 16:04:27 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q35G3wHq013875; Thu, 5 Apr 2012 11:03:58 -0500 Received: from DFLE71.ent.ti.com (dfle71.ent.ti.com [128.247.5.62]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q35G3wqF026252; Thu, 5 Apr 2012 11:03:58 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle71.ent.ti.com (128.247.5.62) with Microsoft SMTP Server id 14.1.323.3; Thu, 5 Apr 2012 11:03:57 -0500 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with SMTP id q35G3qpZ021145; Thu, 5 Apr 2012 11:03:53 -0500 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id EBD77158002; Thu, 5 Apr 2012 21:33:51 +0530 (IST) Received: from linux-psp-server.india.ext.ti.com (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id q35G3pq05209; Thu, 5 Apr 2012 21:33:51 +0530 (IST) From: Afzal Mohammed To: , , , , , , , , , , , , , , Subject: [PATCH v3 4/9] ARM: OMAP2+: gpmc-nand: populate gpmc configs Date: Thu, 5 Apr 2012 21:16:23 +0530 Message-ID: <6c120ab77d0900a6f977246bc58fb37c62280371.1333640054.git.afzal@ti.com> X-Mailer: git-send-email 1.7.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.152 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Afzal Mohammed X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Currently gpmc is configured in platform for nand. As configuring gpmc has been moved to gpmc driver, populate details needed for the driver to configure gpmc. gpmc driver would configure based on this information. Signed-off-by: Afzal Mohammed --- arch/arm/mach-omap2/gpmc-nand.c | 97 ++++++++++++++------------------ arch/arm/plat-omap/include/plat/nand.h | 8 ++- 2 files changed, 48 insertions(+), 57 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 386dec8..85de31f 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -21,24 +21,38 @@ #include #include -static struct resource gpmc_nand_resource = { - .flags = IORESOURCE_MEM, + +#define GPMC_NAND_CONFIG_NUM 4 +#define IDX_DEV_SIZE 2 +#define IDX_RDY_BSY 3 + +static struct gpmc_config gpmc_nand_config[GPMC_NAND_CONFIG_NUM] = { + { GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND}, + { GPMC_CONFIG_WP, 0}, }; -static struct platform_device gpmc_nand_device = { +static struct gpmc_cs_data gpmc_nand_cs_info = { + .config = gpmc_nand_config, + .num_config = ARRAY_SIZE(gpmc_nand_config), + .irq_flags = GPMC_IRQ_FIFOEVENT | GPMC_IRQ_TERMINALCOUNT, +}; + +static struct gpmc_device_pdata gpmc_nand_info = { .name = "omap2-nand", .id = 0, - .num_resources = 1, - .resource = &gpmc_nand_resource, + .cs_data = &gpmc_nand_cs_info, + .num_cs = 1, }; -static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) -{ - struct gpmc_timings t; - int err; +static struct gpmc_timings t; - if (!gpmc_nand_data->gpmc_t) +static struct gpmc_timings * +gpmc_nand_retime(struct omap_nand_platform_data *gpmc_nand_data) +{ + if (!gpmc_nand_data->gpmc_t) { + pr_warn("gpmc timings not provided\n"); return 0; + } memset(&t, 0, sizeof(t)); t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk; @@ -68,56 +82,31 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off); t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); - /* Configure GPMC */ - if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) - gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); - else - gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); - gpmc_cs_configure(gpmc_nand_data->cs, - GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); - if (err) - return err; - - return 0; + return &t; } -int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) +struct gpmc_device_pdata * +__init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) { - int err = 0; - struct device *dev = &gpmc_nand_device.dev; + gpmc_nand_info.pdata = gpmc_nand_data; + gpmc_nand_info.pdata_size = sizeof(*gpmc_nand_data); - gpmc_nand_device.dev.platform_data = gpmc_nand_data; + gpmc_nand_cs_info.cs = gpmc_nand_data->cs; + gpmc_nand_cs_info.mem_size = NAND_IO_SIZE; - err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, - &gpmc_nand_data->phys_base); - if (err < 0) { - dev_err(dev, "Cannot request GPMC CS\n"); - return err; - } + gpmc_nand_cs_info.timing = gpmc_nand_retime(gpmc_nand_data); - /* Set timings in GPMC */ - err = omap2_nand_gpmc_retime(gpmc_nand_data); - if (err < 0) { - dev_err(dev, "Unable to set gpmc timings: %d\n", err); - return err; - } - - /* Enable RD PIN Monitoring Reg */ - if (gpmc_nand_data->dev_ready) { - gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); - } - - err = platform_device_register(&gpmc_nand_device); - if (err < 0) { - dev_err(dev, "Unable to register NAND device\n"); - goto out_free_cs; - } - - return 0; + gpmc_nand_config[IDX_DEV_SIZE].cmd = GPMC_CONFIG_DEV_SIZE; + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) + gpmc_nand_config[IDX_DEV_SIZE].val = 1; + else + gpmc_nand_config[IDX_DEV_SIZE].val = 0; -out_free_cs: - gpmc_cs_free(gpmc_nand_data->cs); + gpmc_nand_config[IDX_RDY_BSY].cmd = GPMC_CONFIG_RDY_BSY; + if (gpmc_nand_data->dev_ready) + gpmc_nand_config[IDX_RDY_BSY].val = 1; + else + gpmc_nand_config[IDX_RDY_BSY].val = 0; - return err; + return &gpmc_nand_info; } diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 86e4d9c..30c61c9 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -36,10 +36,12 @@ struct omap_nand_platform_data { #define NAND_IO_SIZE 4 #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) -extern int gpmc_nand_init(struct omap_nand_platform_data *d); +extern struct gpmc_device_pdata * +gpmc_nand_init(struct omap_nand_platform_data *d); #else -static inline int gpmc_nand_init(struct omap_nand_platform_data *d) +static inline struct gpmc_device_pdata * +gpmc_nand_init(struct omap_nand_platform_data *d) { - return 0; + return NULL; } #endif