From patchwork Fri Mar 30 17:05:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 83FA0B6EF3 for ; Sat, 31 Mar 2012 04:07:27 +1100 (EST) Received: from localhost ([::1]:53511 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDfIL-0005U9-92 for incoming@patchwork.ozlabs.org; Fri, 30 Mar 2012 13:07:25 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDfHU-0003Zm-S2 for qemu-devel@nongnu.org; Fri, 30 Mar 2012 13:06:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDfHN-0002nM-MX for qemu-devel@nongnu.org; Fri, 30 Mar 2012 13:06:32 -0400 Received: from mail-qa0-f52.google.com ([209.85.216.52]:48960) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDfHN-0002mT-FP for qemu-devel@nongnu.org; Fri, 30 Mar 2012 13:06:25 -0400 Received: by mail-qa0-f52.google.com with SMTP id g40so527894qab.4 for ; Fri, 30 Mar 2012 10:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=RzQgMXhRUC9MhBhv38G8+5h0izJLssyDrql5K9mCSqM=; b=DnP3kcegYusuTeoeSfa/sw3iD3d4o7CVMYYhIuKc6V4L24Kf1sn2WccXCyBttWDL0S RoWsROnLxNQDYXy/xjHjZ5k/EKfNOaKRQRzNl4SVwUAyYHQY/JCS7duVrOuQ2A6DDlpn b0SF38TfwOAAt5pa70raU47iG5Npn3itOqNe4hZF8aACIH7Xrv1nE+NF9dOi0kn7E00f 2QRVq5AyakjkEYDIIAs6GdncjzIv/cnfuHGUK4B0CI/BPj+cEqx8YycE8Q07BW/p+GdQ TwlY3ZIesi54vDHnMP581PE3Jp8mTHvwEfLg/6QyOWjf+0eibBken5n8SLxnAJ9/aOOz Gi6A== Received: by 10.224.208.1 with SMTP id ga1mr6642337qab.21.1333127184838; Fri, 30 Mar 2012 10:06:24 -0700 (PDT) Received: from pebble.com ([200.7.43.190]) by mx.google.com with ESMTPS id fq1sm19227716qab.10.2012.03.30.10.06.23 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 10:06:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 30 Mar 2012 13:05:41 -0400 Message-Id: <1333127144-7088-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1333127144-7088-1-git-send-email-rth@twiddle.net> References: <1333127144-7088-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.216.52 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 2/5] target-mips: Fix MIPS_DEBUG. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The macro uses the DisasContext. Pass it around as needed. Signed-off-by: Richard Henderson --- target-mips/translate.c | 74 ++++++++++++++++++++++++----------------------- 1 files changed, 38 insertions(+), 36 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 85dd65a..f18df40 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1413,7 +1413,8 @@ static void gen_arith_imm (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Logic with immediate operand */ -static void gen_logic_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm) +static void gen_logic_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) { target_ulong uimm; const char *opn = "imm logic"; @@ -1456,7 +1457,8 @@ static void gen_logic_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int1 } /* Set on less than with immediate operand */ -static void gen_slt_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm) +static void gen_slt_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) { target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ const char *opn = "imm arith"; @@ -1757,7 +1759,8 @@ static void gen_arith (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } /* Conditional move */ -static void gen_cond_move (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt) +static void gen_cond_move(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "cond move"; int l1; @@ -1795,7 +1798,8 @@ static void gen_cond_move (CPUMIPSState *env, uint32_t opc, int rd, int rs, int } /* Logic */ -static void gen_logic (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt) +static void gen_logic(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "logic"; @@ -1856,7 +1860,8 @@ static void gen_logic (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt) } /* Set on lower than */ -static void gen_slt (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt) +static void gen_slt(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "slt"; TCGv t0, t1; @@ -8756,10 +8761,10 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx, gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm); break; case M16_OPC_SLTI: - gen_slt_imm(env, OPC_SLTI, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm); break; case M16_OPC_SLTIU: - gen_slt_imm(env, OPC_SLTIU, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm); break; case M16_OPC_I8: switch (funct) { @@ -8970,15 +8975,13 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, case M16_OPC_SLTI: { int16_t imm = (uint8_t) ctx->opcode; - - gen_slt_imm(env, OPC_SLTI, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm); } break; case M16_OPC_SLTIU: { int16_t imm = (uint8_t) ctx->opcode; - - gen_slt_imm(env, OPC_SLTIU, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm); } break; case M16_OPC_I8: @@ -9053,8 +9056,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, case M16_OPC_CMPI: { int16_t imm = (uint8_t) ctx->opcode; - - gen_logic_imm(env, OPC_XORI, 24, rx, imm); + gen_logic_imm(env, ctx, OPC_XORI, 24, rx, imm); } break; #if defined(TARGET_MIPS64) @@ -9166,10 +9168,10 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, } break; case RR_SLT: - gen_slt(env, OPC_SLT, 24, rx, ry); + gen_slt(env, ctx, OPC_SLT, 24, rx, ry); break; case RR_SLTU: - gen_slt(env, OPC_SLTU, 24, rx, ry); + gen_slt(env, ctx, OPC_SLTU, 24, rx, ry); break; case RR_BREAK: generate_exception(ctx, EXCP_BREAK); @@ -9190,22 +9192,22 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, break; #endif case RR_CMP: - gen_logic(env, OPC_XOR, 24, rx, ry); + gen_logic(env, ctx, OPC_XOR, 24, rx, ry); break; case RR_NEG: gen_arith(env, ctx, OPC_SUBU, rx, 0, ry); break; case RR_AND: - gen_logic(env, OPC_AND, rx, rx, ry); + gen_logic(env, ctx, OPC_AND, rx, rx, ry); break; case RR_OR: - gen_logic(env, OPC_OR, rx, rx, ry); + gen_logic(env, ctx, OPC_OR, rx, rx, ry); break; case RR_XOR: - gen_logic(env, OPC_XOR, rx, rx, ry); + gen_logic(env, ctx, OPC_XOR, rx, rx, ry); break; case RR_NOT: - gen_logic(env, OPC_NOR, rx, ry, 0); + gen_logic(env, ctx, OPC_NOR, rx, ry, 0); break; case RR_MFHI: gen_HILO(ctx, OPC_MFHI, rx); @@ -9827,7 +9829,7 @@ static void gen_andi16 (CPUMIPSState *env, DisasContext *ctx) int rs = mmreg(uMIPS_RS(ctx->opcode)); int encoded = ZIMM(ctx->opcode, 0, 4); - gen_logic_imm(env, OPC_ANDI, rd, rs, decoded_imm[encoded]); + gen_logic_imm(env, ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); } static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, @@ -9889,25 +9891,25 @@ static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_bran case NOT16 + 1: case NOT16 + 2: case NOT16 + 3: - gen_logic(env, OPC_NOR, rd, rs, 0); + gen_logic(env, ctx, OPC_NOR, rd, rs, 0); break; case XOR16 + 0: case XOR16 + 1: case XOR16 + 2: case XOR16 + 3: - gen_logic(env, OPC_XOR, rd, rd, rs); + gen_logic(env, ctx, OPC_XOR, rd, rd, rs); break; case AND16 + 0: case AND16 + 1: case AND16 + 2: case AND16 + 3: - gen_logic(env, OPC_AND, rd, rd, rs); + gen_logic(env, ctx, OPC_AND, rd, rd, rs); break; case OR16 + 0: case OR16 + 1: case OR16 + 2: case OR16 + 3: - gen_logic(env, OPC_OR, rd, rd, rs); + gen_logic(env, ctx, OPC_OR, rd, rd, rs); break; case LWM16 + 0: case LWM16 + 1: @@ -10707,7 +10709,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case XOR32: mips32_op = OPC_XOR; do_logic: - gen_logic(env, mips32_op, rd, rs, rt); + gen_logic(env, ctx, mips32_op, rd, rs, rt); break; /* Set less than */ case SLT: @@ -10716,7 +10718,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case SLTU: mips32_op = OPC_SLTU; do_slt: - gen_slt(env, mips32_op, rd, rs, rt); + gen_slt(env, ctx, mips32_op, rd, rs, rt); break; default: goto pool32a_invalid; @@ -10732,7 +10734,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case MOVZ: mips32_op = OPC_MOVZ; do_cmov: - gen_cond_move(env, mips32_op, rd, rs, rt); + gen_cond_move(env, ctx, mips32_op, rd, rs, rt); break; case LWXS: gen_ldxs(ctx, rs, rt, rd); @@ -11144,7 +11146,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, target. */ break; case LUI: - gen_logic_imm(env, OPC_LUI, rs, -1, imm); + gen_logic_imm(env, ctx, OPC_LUI, rs, -1, imm); break; case SYNCI: break; @@ -11263,7 +11265,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case ANDI32: mips32_op = OPC_ANDI; do_logici: - gen_logic_imm(env, mips32_op, rt, rs, imm); + gen_logic_imm(env, ctx, mips32_op, rt, rs, imm); break; /* Set less than immediate */ @@ -11273,7 +11275,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, case SLTIU32: mips32_op = OPC_SLTIU; do_slti: - gen_slt_imm(env, mips32_op, rt, rs, imm); + gen_slt_imm(env, ctx, mips32_op, rt, rs, imm); break; case JALX32: offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; @@ -11750,7 +11752,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_MOVZ: check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32 | INSN_LOONGSON2E | INSN_LOONGSON2F); - gen_cond_move(env, op1, rd, rs, rt); + gen_cond_move(env, ctx, op1, rd, rs, rt); break; case OPC_ADD ... OPC_SUBU: gen_arith(env, ctx, op1, rd, rs, rt); @@ -11777,13 +11779,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_SLT: /* Set on less than */ case OPC_SLTU: - gen_slt(env, op1, rd, rs, rt); + gen_slt(env, ctx, op1, rd, rs, rt); break; case OPC_AND: /* Logic*/ case OPC_OR: case OPC_NOR: case OPC_XOR: - gen_logic(env, op1, rd, rs, rt); + gen_logic(env, ctx, op1, rd, rs, rt); break; case OPC_MULT ... OPC_DIVU: if (sa) { @@ -12184,13 +12186,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; case OPC_SLTI: /* Set on less than with immediate opcode */ case OPC_SLTIU: - gen_slt_imm(env, op, rt, rs, imm); + gen_slt_imm(env, ctx, op, rt, rs, imm); break; case OPC_ANDI: /* Arithmetic with immediate opcode */ case OPC_LUI: case OPC_ORI: case OPC_XORI: - gen_logic_imm(env, op, rt, rs, imm); + gen_logic_imm(env, ctx, op, rt, rs, imm); break; case OPC_J ... OPC_JAL: /* Jump */ offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;