From patchwork Fri Mar 30 10:26:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 149628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1D295B6EEF for ; Fri, 30 Mar 2012 22:20:56 +1100 (EST) Received: from localhost ([::1]:53898 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDZ2w-0004RN-Ex for incoming@patchwork.ozlabs.org; Fri, 30 Mar 2012 06:27:06 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDZ2Y-0003pn-NY for qemu-devel@nongnu.org; Fri, 30 Mar 2012 06:26:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDZ2W-0003rE-KN for qemu-devel@nongnu.org; Fri, 30 Mar 2012 06:26:42 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:51100) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDZ2W-0003r6-B4 for qemu-devel@nongnu.org; Fri, 30 Mar 2012 06:26:40 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SDZ28-0000s0-JM; Fri, 30 Mar 2012 11:26:16 +0100 From: Peter Maydell To: Blue Swirl , Aurelien Jarno , Paul Brook Date: Fri, 30 Mar 2012 11:26:16 +0100 Message-Id: <1333103176-3313-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1333103176-3313-1-git-send-email-peter.maydell@linaro.org> References: <1333103176-3313-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 3/3] ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Andrew Towers This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registers with a test for a new feature flag ARM_FEATURE_MVFR, and sets this feature for all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu does not support ARM1156 at this time.) MVFR0 and MVFR1 were introduced in ARM1136JF-S r1p0 (ARMv6K, VFPv2) and are present in ARM1156T2F-S (non-v6K), ARM1176JZF-S, ARM11MPCore and newer cores. Reference: ARM DDI 0211H, 0290G, 0301H, 0360E. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Ffbefjag.html Without this change, the linux kernel will not boot with VFP support enabled under ARM1176 system emulation, due to the unconditional use of MVFR1 at the end of vfp_init() in arch/arm/vfp/vfpmodule.c: VFP support v0.3: implemetor 41 architecture 1 part 20 variant b rev 5 Internal error: Oops - undefined instruction: 0 [#1] Signed-off-by: Andrew Towers Reviewed-by: Andreas Färber Signed-off-by: Peter Maydell --- target-arm/cpu.h | 1 + target-arm/helper.c | 1 + target-arm/translate.c | 2 +- 3 files changed, 3 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a68df61..e176c5f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -382,6 +382,7 @@ enum arm_features { ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ ARM_FEATURE_GENERIC_TIMER, + ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index dd8e306..d974b57 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -254,6 +254,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) } if (arm_feature(env, ARM_FEATURE_V6K)) { set_feature(env, ARM_FEATURE_V6); + set_feature(env, ARM_FEATURE_MVFR); } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); diff --git a/target-arm/translate.c b/target-arm/translate.c index 81725d1..46d1d3e 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2906,7 +2906,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) case ARM_VFP_MVFR0: case ARM_VFP_MVFR1: if (IS_USER(s) - || !arm_feature(env, ARM_FEATURE_VFP3)) + || !arm_feature(env, ARM_FEATURE_MVFR)) return 1; tmp = load_cpu_field(vfp.xregs[rn]); break;