Patchwork [U-Boot,V2,22/24] SPEAr: Correct SoC ID offset in misc configuration space

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Submitter Amit Virdi
Date March 30, 2012, 6:55 a.m.
Message ID <8b789a3197fc7ec7e9b38cc3ee3dd7e807de3543.1333090212.git.amit.virdi@st.com>
Download mbox | patch
Permalink /patch/149572/
State Superseded
Delegated to: Stefan Roese
Headers show

Comments

Amit Virdi - March 30, 2012, 6:55 a.m.
From: Shiraz Hashim <shiraz.hashim@st.com>

SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
---
 arch/arm/include/asm/arch-spear/spr_misc.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Patch

diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index 384944d..b8fcf49 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -37,7 +37,7 @@  struct misc_regs {
 	u32 amba_clk_cfg;	/* 0x24 */
 	u32 periph_clk_cfg;	/* 0x28 */
 	u32 periph1_clken;	/* 0x2C */
-	u32 periph2_clken;	/* 0x30 */
+	u32 soc_core_id;	/* 0x30 */
 	u32 ras_clken;		/* 0x34 */
 	u32 periph1_rst;	/* 0x38 */
 	u32 periph2_rst;	/* 0x3C */