diff mbox

[net-next,v3,5/5] r8169: support RTL8411

Message ID 1333090086-1815-1-git-send-email-hayeswang@realtek.com
State Awaiting Upstream, archived
Delegated to: David Miller
Headers show

Commit Message

Hayes Wang March 30, 2012, 6:48 a.m. UTC 
Support the new chip RTL8411.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
---
 drivers/net/ethernet/realtek/r8169.c |  140 +++++++++++++++++++++++++++++++++-
 1 files changed, 138 insertions(+), 2 deletions(-)

Comments

Francois Romieu March 30, 2012, 7:25 a.m. UTC | #1 
Hayes Wang <hayeswang@realtek.com> :
> Support the new chip RTL8411.
> 
> Signed-off-by: Hayes Wang <hayeswang@realtek.com>

I do not see any change related to rtl_init_jumbo_ops. If NULL is ok for
jumbo_{enable / disable}, it deserves to be outlined in the commit
message.

No reviewer can figure what's going on otherwise.
Hayes Wang April 5, 2012, 6:06 a.m. UTC | #2 
Francois Romieu [mailto:romieu@fr.zoreil.com] 
> Sent: Friday, March 30, 2012 3:25 PM
> To: Hayeswang
> Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH net-next v3 5/5] r8169: support RTL8411
> 
> Hayes Wang <hayeswang@realtek.com> :
> > Support the new chip RTL8411.
> > 
> > Signed-off-by: Hayes Wang <hayeswang@realtek.com>
> 
> I do not see any change related to rtl_init_jumbo_ops. If 
> NULL is ok for
> jumbo_{enable / disable}, it deserves to be outlined in the commit
> message.
> 
> No reviewer can figure what's going on otherwise.
> 

There is nothing to do for rtl_init_jumbo_ops. It is all right for keeping NULL.
Do I need to resend this patch?
 
Best Regards,
Hayes

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Francois Romieu April 5, 2012, 8:37 a.m. UTC | #3 
hayeswang <hayeswang@realtek.com> :
[...]
> There is nothing to do for rtl_init_jumbo_ops. It is all right for keeping
> NULL.

Ok, I'll add it to the commit message for future reference.

> Do I need to resend this patch?

No, I'll give it a short testing and forward to David.

We have a few weeks of net-next head. If there are further changes in sight,
you may consider planning for those before the cycle ends. Otherwise they
will experience a complete kernel cycle delay.

Thanks.
Francois Romieu April 9, 2012, 6:02 p.m. UTC | #4 
Francois Romieu <romieu@fr.zoreil.com> :
> hayeswang <hayeswang@realtek.com> :
> [...]
> > There is nothing to do for rtl_init_jumbo_ops. It is all right for keeping
> > NULL.
> 
> Ok, I'll add it to the commit message for future reference.
> 
> > Do I need to resend this patch?
> 
> No, I'll give it a short testing and forward to David.

Rx/Tx is ok, WoL + shutdown is ok but runtime power management is not.

I tried net-next + your patches + cff4c16296754888b6fd8c886bc860a888e20257
("r8169: enable napi on resume.", required for RPM or suspend/resume after
regression in da78dbff2e05630921c551dbbc70a4b7981a8fff).

- set a 8402 and a 8411 in the same test box
- ip addr add ... 
- ip link set dev ... up 
- start ping from remote host
- echo auto > /sys/bus/pci/devices/.../power/control
- unplug cable
  - ping stops flowing
  - cat /sys/bus/pci/devices/.../power/runtime_status
    -> "active"
- plug cable
  -> RPM status does not change, no link, no packet, no fun.

I have tried the same with a built-in 8168b (XID 18000000).
-> RPM status changes, link recovers, packets flow.

The 8168b is a bit special, so I swapped the 8411 for a 8102e (XID 04a00000).
It resumed correctly as well.

Any idea ?
Hayes Wang April 16, 2012, 6:58 a.m. UTC | #5 
Francois Romieu [mailto:romieu@fr.zoreil.com] 
> Sent: Tuesday, April 10, 2012 2:02 AM
> To: Hayeswang
> Cc: netdev@vger.kernel.org
> Subject: Re: [PATCH net-next v3 5/5] r8169: support RTL8411
[...]
> 
> Rx/Tx is ok, WoL + shutdown is ok but runtime power management is not.
> 
[...]
> 
> - set a 8402 and a 8411 in the same test box
> - ip addr add ... 
> - ip link set dev ... up 
> - start ping from remote host
> - echo auto > /sys/bus/pci/devices/.../power/control
> - unplug cable
>   - ping stops flowing
>   - cat /sys/bus/pci/devices/.../power/runtime_status
>     -> "active"
> - plug cable
>   -> RPM status does not change, no link, no packet, no fun.
> 

The 8111C and the later chips have to set Config2 (0x53) bit 5 to enable PME
status for WOL.
Besides, the config1 (0x52) bit 0 is the read-only. Maybe you could skip setting
it.
 
Best Regards,
Hayes

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Francois Romieu April 17, 2012, 11:05 a.m. UTC | #6 
hayeswang <hayeswang@realtek.com> :
[...]
> The 8111C and the later chips have to set Config2 (0x53) bit 5 to enable PME
> status for WOL.

Thanks, 8402 and 8411 work way better now.

> Besides, the config1 (0x52) bit 0 is the read-only. Maybe you could skip
> setting it.

I have done it as well.
diff mbox

Patch

diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 3ba49dc..dcc1ec5 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -46,6 +46,7 @@ 
 #define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"
 #define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"
 #define FIRMWARE_8402_1		"rtl_nic/rtl8402-1.fw"
+#define FIRMWARE_8411_1		"rtl_nic/rtl8411-1.fw"
 
 #ifdef RTL8169_DEBUG
 #define assert(expr) \
@@ -136,6 +137,7 @@  enum mac_version {
 	RTL_GIGA_MAC_VER_35,
 	RTL_GIGA_MAC_VER_36,
 	RTL_GIGA_MAC_VER_37,
+	RTL_GIGA_MAC_VER_38,
 	RTL_GIGA_MAC_NONE   = 0xff,
 };
 
@@ -251,6 +253,9 @@  static const struct {
 	[RTL_GIGA_MAC_VER_37] =
 		_R("RTL8402",		RTL_TD_1, FIRMWARE_8402_1,
 							JUMBO_1K, true),
+	[RTL_GIGA_MAC_VER_38] =
+		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_1,
+							JUMBO_9K, false),
 };
 #undef _R
 
@@ -783,6 +788,7 @@  MODULE_FIRMWARE(FIRMWARE_8105E_1);
 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 MODULE_FIRMWARE(FIRMWARE_8402_1);
+MODULE_FIRMWARE(FIRMWARE_8411_1);
 
 static void rtl_lock_work(struct rtl8169_private *tp)
 {
@@ -1262,7 +1268,8 @@  static void rtl_link_chg_patch(struct rtl8169_private *tp)
 	if (!netif_running(dev))
 		return;
 
-	if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
+	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
+	    tp->mac_version == RTL_GIGA_MAC_VER_38) {
 		if (RTL_R8(PHYstatus) & _1000bpsF) {
 			rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
 				      0x00000011, ERIAR_EXGMAC);
@@ -1867,6 +1874,7 @@  static void rtl8169_get_mac_version(struct rtl8169_private *tp,
 		int mac_version;
 	} mac_info[] = {
 		/* 8168F family. */
+		{ 0x7c800000, 0x48800000,	RTL_GIGA_MAC_VER_38 },
 		{ 0x7cf00000, 0x48100000,	RTL_GIGA_MAC_VER_36 },
 		{ 0x7cf00000, 0x48000000,	RTL_GIGA_MAC_VER_35 },
 
@@ -3084,6 +3092,104 @@  static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
 	rtl8168f_hw_phy_config(tp);
 }
 
+static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
+{
+	void __iomem *ioaddr = tp->mmio_addr;
+	static const struct phy_reg phy_reg_init[] = {
+		/* Channel estimation fine tune */
+		{ 0x1f, 0x0003 },
+		{ 0x09, 0xa20f },
+		{ 0x1f, 0x0000 },
+
+		/* Modify green table for giga & fnet */
+		{ 0x1f, 0x0005 },
+		{ 0x05, 0x8b55 },
+		{ 0x06, 0x0000 },
+		{ 0x05, 0x8b5e },
+		{ 0x06, 0x0000 },
+		{ 0x05, 0x8b67 },
+		{ 0x06, 0x0000 },
+		{ 0x05, 0x8b70 },
+		{ 0x06, 0x0000 },
+		{ 0x1f, 0x0000 },
+		{ 0x1f, 0x0007 },
+		{ 0x1e, 0x0078 },
+		{ 0x17, 0x0000 },
+		{ 0x19, 0x00aa },
+		{ 0x1f, 0x0000 },
+
+		/* Modify green table for 10M */
+		{ 0x1f, 0x0005 },
+		{ 0x05, 0x8b79 },
+		{ 0x06, 0xaa00 },
+		{ 0x1f, 0x0000 },
+
+		/* Disable hiimpedance detection (RTCT) */
+		{ 0x1f, 0x0003 },
+		{ 0x01, 0x328a },
+		{ 0x1f, 0x0000 }
+	};
+
+
+	rtl_apply_firmware(tp);
+
+	rtl8168f_hw_phy_config(tp);
+
+	/* Improve 2-pair detection performance */
+	rtl_writephy(tp, 0x1f, 0x0005);
+	rtl_writephy(tp, 0x05, 0x8b85);
+	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
+	rtl_writephy(tp, 0x1f, 0x0000);
+
+	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+
+	/* Modify green table for giga */
+	rtl_writephy(tp, 0x1f, 0x0005);
+	rtl_writephy(tp, 0x05, 0x8b54);
+	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
+	rtl_writephy(tp, 0x05, 0x8b5d);
+	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
+	rtl_writephy(tp, 0x05, 0x8a7c);
+	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
+	rtl_writephy(tp, 0x05, 0x8a7f);
+	rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
+	rtl_writephy(tp, 0x05, 0x8a82);
+	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
+	rtl_writephy(tp, 0x05, 0x8a85);
+	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
+	rtl_writephy(tp, 0x05, 0x8a88);
+	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
+	rtl_writephy(tp, 0x1f, 0x0000);
+
+	/* uc same-seed solution */
+	rtl_writephy(tp, 0x1f, 0x0005);
+	rtl_writephy(tp, 0x05, 0x8b85);
+	rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
+	rtl_writephy(tp, 0x1f, 0x0000);
+
+	/* eee setting */
+	rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
+	rtl_writephy(tp, 0x1f, 0x0005);
+	rtl_writephy(tp, 0x05, 0x8b85);
+	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
+	rtl_writephy(tp, 0x1f, 0x0004);
+	rtl_writephy(tp, 0x1f, 0x0007);
+	rtl_writephy(tp, 0x1e, 0x0020);
+	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
+	rtl_writephy(tp, 0x1f, 0x0000);
+	rtl_writephy(tp, 0x0d, 0x0007);
+	rtl_writephy(tp, 0x0e, 0x003c);
+	rtl_writephy(tp, 0x0d, 0x4007);
+	rtl_writephy(tp, 0x0e, 0x0000);
+	rtl_writephy(tp, 0x0d, 0x0000);
+
+	/* Green feature */
+	rtl_writephy(tp, 0x1f, 0x0003);
+	rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
+	rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
+	rtl_writephy(tp, 0x1f, 0x0000);
+}
+
 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
 {
 	static const struct phy_reg phy_reg_init[] = {
@@ -3238,6 +3344,10 @@  static void rtl_hw_phy_config(struct net_device *dev)
 		rtl8402_hw_phy_config(tp);
 		break;
 
+	case RTL_GIGA_MAC_VER_38:
+		rtl8411_hw_phy_config(tp);
+		break;
+
 	default:
 		break;
 	}
@@ -3476,6 +3586,7 @@  static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
 	case RTL_GIGA_MAC_VER_33:
 	case RTL_GIGA_MAC_VER_34:
 	case RTL_GIGA_MAC_VER_37:
+	case RTL_GIGA_MAC_VER_38:
 		RTL_W32(RxConfig, RTL_R32(RxConfig) |
 			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
 		break;
@@ -3722,6 +3833,7 @@  static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
 	case RTL_GIGA_MAC_VER_34:
 	case RTL_GIGA_MAC_VER_35:
 	case RTL_GIGA_MAC_VER_36:
+	case RTL_GIGA_MAC_VER_38:
 		ops->down	= r8168_pll_power_down;
 		ops->up		= r8168_pll_power_up;
 		break;
@@ -4008,7 +4120,8 @@  static void rtl8169_hw_reset(struct rtl8169_private *tp)
 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
 	           tp->mac_version == RTL_GIGA_MAC_VER_35 ||
 	           tp->mac_version == RTL_GIGA_MAC_VER_36 ||
-	           tp->mac_version == RTL_GIGA_MAC_VER_37) {
+	           tp->mac_version == RTL_GIGA_MAC_VER_37 ||
+	           tp->mac_version == RTL_GIGA_MAC_VER_38) {
 		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
 		while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
 			udelay(100);
@@ -4339,6 +4452,7 @@  static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
 		break;
 
 	case RTL_GIGA_MAC_VER_37:
+	case RTL_GIGA_MAC_VER_38:
 		ops->write	= r8402_csi_write;
 		ops->read	= r8402_csi_read;
 		break;
@@ -4727,6 +4841,24 @@  static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
 	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
 }
 
+static void rtl_hw_start_8411(struct rtl8169_private *tp)
+{
+	void __iomem *ioaddr = tp->mmio_addr;
+	static const struct ephy_info e_info_8168f_1[] = {
+		{ 0x06, 0x00c0,	0x0020 },
+		{ 0x0f, 0xffff,	0x5200 },
+		{ 0x1e, 0x0000,	0x4000 },
+		{ 0x19, 0x0000,	0x0224 }
+	};
+
+	rtl_hw_start_8168f(tp);
+
+	rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
+
+	rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000,
+		     ERIAR_EXGMAC);
+}
+
 static void rtl_hw_start_8168(struct net_device *dev)
 {
 	struct rtl8169_private *tp = netdev_priv(dev);
@@ -4824,6 +4956,10 @@  static void rtl_hw_start_8168(struct net_device *dev)
 		rtl_hw_start_8168f_1(tp);
 		break;
 
+	case RTL_GIGA_MAC_VER_38:
+		rtl_hw_start_8411(tp);
+		break;
+
 	default:
 		printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
 			dev->name, tp->mac_version);