@@ -1839,6 +1839,417 @@ uint32_t helper_preceu_ph_qbra(uint32_t rt)
return rd;
}
+/** DSP GPR-Based Shift Sub-class insns **/
+uint32_t helper_shll_qb(CPUMIPSState *env, int sa, uint32_t rt)
+{
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = mipsdsp_lshift8(env, rt3, sa);
+ tempC = mipsdsp_lshift8(env, rt2, sa);
+ tempB = mipsdsp_lshift8(env, rt1, sa);
+ tempA = mipsdsp_lshift8(env, rt0, sa);
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | ((uint32_t)tempA);
+
+ return rd;
+}
+
+uint32_t helper_shllv_qb(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs2_0;
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs2_0 = rs & 0x07;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = mipsdsp_lshift8(env, rt3, rs2_0);
+ tempC = mipsdsp_lshift8(env, rt2, rs2_0);
+ tempB = mipsdsp_lshift8(env, rt1, rs2_0);
+ tempA = mipsdsp_lshift8(env, rt0, rs2_0);
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shll_ph(CPUMIPSState *env, int sa, uint32_t rt)
+{
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_lshift16(env, rth, sa);
+ tempA = mipsdsp_lshift16(env, rtl, sa);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shllv_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3_0;
+ uint16_t rth, rtl, tempB, tempA;
+ uint32_t rd;
+
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ rs3_0 = rs & 0x0F;
+
+ tempB = mipsdsp_lshift16(env, rth, rs3_0);
+ tempA = mipsdsp_lshift16(env, rtl, rs3_0);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shll_s_ph(CPUMIPSState *env, int sa, uint32_t rt)
+{
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_sat16_lshift(env, rth, sa);
+ tempA = mipsdsp_sat16_lshift(env, rtl, sa);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shllv_s_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3_0;
+ uint16_t rth, rtl, tempB, tempA;
+ uint32_t rd;
+
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ rs3_0 = rs & 0x0F;
+
+ tempB = mipsdsp_sat16_lshift(env, rth, rs3_0);
+ tempA = mipsdsp_sat16_lshift(env, rtl, rs3_0);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shll_s_w(CPUMIPSState *env, int sa, uint32_t rt)
+{
+ uint32_t temp, rd;
+
+ temp = mipsdsp_sat32_lshift(env, rt, sa);
+ rd = temp;
+
+ return rd;
+}
+
+uint32_t helper_shllv_s_w(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs4_0;
+ uint32_t rd;
+
+ rs4_0 = rs & 0x1F;
+ rd = mipsdsp_sat32_lshift(env, rt, rs4_0);
+
+ return rd;
+}
+
+uint32_t helper_shrl_qb(int sa, uint32_t rt)
+{
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = mipsdsp_rshift8(rt3, sa);
+ tempC = mipsdsp_rshift8(rt2, sa);
+ tempB = mipsdsp_rshift8(rt1, sa);
+ tempA = mipsdsp_rshift8(rt0, sa);
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shrlv_qb(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs2_0;
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs2_0 = rs & 0x07;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = mipsdsp_rshift8(rt3, rs2_0);
+ tempC = mipsdsp_rshift8(rt2, rs2_0);
+ tempB = mipsdsp_rshift8(rt1, rs2_0);
+ tempA = mipsdsp_rshift8(rt0, rs2_0);
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shrl_ph(int sa, uint32_t rt)
+{
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = rth >> sa;
+ tempA = rtl >> sa;
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shrlv_ph(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3_0;
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rs3_0 = rs & 0x0F;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = rth >> rs3_0;
+ tempA = rtl >> rs3_0;
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shra_qb(int sa, uint32_t rt)
+{
+ int8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = rt3 >> sa;
+ tempC = rt2 >> sa;
+ tempB = rt1 >> sa;
+ tempA = rt0 >> sa;
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shra_r_qb(int sa, uint32_t rt)
+{
+ int8_t rt3, rt2, rt1, rt0;
+ uint16_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ if (sa == 0) {
+ tempD = rt3 & 0x00FF;
+ tempC = rt2 & 0x00FF;
+ tempB = rt1 & 0x00FF;
+ tempA = rt0 & 0x00FF;
+ } else {
+ tempD = ((int16_t)rt3 >> (sa - 1)) + 1;
+ tempC = ((int16_t)rt2 >> (sa - 1)) + 1;
+ tempB = ((int16_t)rt1 >> (sa - 1)) + 1;
+ tempA = ((int16_t)rt0 >> (sa - 1)) + 1;
+ }
+
+ rd = ((uint32_t)((tempD >> 1) & 0x00FF) << 24) | \
+ ((uint32_t)((tempC >> 1) & 0x00FF) << 16) | \
+ ((uint32_t)((tempB >> 1) & 0x00FF) << 8) | \
+ (uint32_t)((tempA >> 1) & 0x00FF) ;
+
+ return rd;
+}
+
+uint32_t helper_shrav_qb(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs2_0;
+ int8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs2_0 = rs & 0x07;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ if (rs2_0 == 0) {
+ tempD = rt3;
+ tempC = rt2;
+ tempB = rt1;
+ tempA = rt0;
+ } else {
+ tempD = rt3 >> rs2_0;
+ tempC = rt2 >> rs2_0;
+ tempB = rt1 >> rs2_0;
+ tempA = rt0 >> rs2_0;
+ }
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shrav_r_qb(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs2_0;
+ int8_t rt3, rt2, rt1, rt0;
+ uint16_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs2_0 = rs & 0x07;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ if (rs2_0 == 0) {
+ tempD = (int16_t)rt3 << 1;
+ tempC = (int16_t)rt2 << 1;
+ tempB = (int16_t)rt1 << 1;
+ tempA = (int16_t)rt0 << 1;
+ } else {
+ tempD = ((int16_t)rt3 >> (rs2_0 - 1)) + 1;
+ tempC = ((int16_t)rt2 >> (rs2_0 - 1)) + 1;
+ tempB = ((int16_t)rt1 >> (rs2_0 - 1)) + 1;
+ tempA = ((int16_t)rt0 >> (rs2_0 - 1)) + 1;
+ }
+
+ rd = ((uint32_t)((tempD >> 1) & 0x00FF) << 24) | \
+ ((uint32_t)((tempC >> 1) & 0x00FF) << 16) | \
+ ((uint32_t)((tempB >> 1) & 0x00FF) << 8) | \
+ (uint32_t)((tempA >> 1) & 0x00FF) ;
+
+ return rd;
+}
+
+uint32_t helper_shra_ph(int sa, uint32_t rt)
+{
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_rashift16(rth, sa);
+ tempA = mipsdsp_rashift16(rtl, sa);
+ rd = ((uint32_t)tempB << 16) | (uint32_t) tempA;
+
+ return rd;
+}
+
+uint32_t helper_shrav_ph(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3_0;
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rs3_0 = rs & 0x0F;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_rashift16(rth, rs3_0);
+ tempA = mipsdsp_rashift16(rtl, rs3_0);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shra_r_ph(int sa, uint32_t rt)
+{
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_rnd16_rashift(rth, sa);
+ tempA = mipsdsp_rnd16_rashift(rtl, sa);
+ rd = ((uint32_t)tempB << 16) | (uint32_t) tempA;
+
+ return rd;
+}
+
+uint32_t helper_shrav_r_ph(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3_0;
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rs3_0 = rs & 0x0F;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_rnd16_rashift(rth, rs3_0);
+ tempA = mipsdsp_rnd16_rashift(rtl, rs3_0);
+
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_shra_r_w(int sa, uint32_t rt)
+{
+ uint32_t rd;
+
+ rd = mipsdsp_rnd32_rashift(rt, sa);
+
+ return rd;
+}
+
+uint32_t helper_shrav_r_w(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs4_0;
+ uint32_t rd;
+
+ rs4_0 = rs & 0x1F;
+ rd = mipsdsp_rnd32_rashift(rt, rs4_0);
+
+ return rd;
+}
+
#undef MIPSDSP_LHI
#undef MIPSDSP_LLO
#undef MIPSDSP_HI
@@ -352,4 +352,28 @@ DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+/* DSP GPR-Based Shift Sub-class insns */
+DEF_HELPER_FLAGS_3(shll_qb, 0, i32, env, int, i32)
+DEF_HELPER_FLAGS_3(shllv_qb, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(shll_ph, 0, i32, env, int, i32)
+DEF_HELPER_FLAGS_3(shllv_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(shll_s_ph, 0, i32, env, int, i32)
+DEF_HELPER_FLAGS_3(shllv_s_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(shll_s_w, 0, i32, env, int, i32)
+DEF_HELPER_FLAGS_3(shllv_s_w, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(shrl_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
+DEF_HELPER_FLAGS_2(shrlv_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(shrl_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
+DEF_HELPER_FLAGS_2(shrlv_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(shra_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
+DEF_HELPER_FLAGS_2(shra_r_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
+DEF_HELPER_FLAGS_2(shrav_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(shrav_r_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(shra_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
+DEF_HELPER_FLAGS_2(shrav_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(shra_r_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
+DEF_HELPER_FLAGS_2(shrav_r_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
+DEF_HELPER_FLAGS_2(shrav_r_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+
#include "def-helper.h"
@@ -321,6 +321,8 @@ enum {
/* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
/* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
+ /* MIPS DSP GPR-Based Shift Sub-class */
+ OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
};
/* BSHFL opcodes */
@@ -424,6 +426,33 @@ enum {
OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
};
+#define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* MIPS DSP GPR-Based Shift Sub-class */
+ OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP,
+ OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
+};
+
/* Coprocessor 0 (rs field) */
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
@@ -12395,6 +12424,91 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
break;
}
break;
+ case OPC_SHLL_QB_DSP:
+ {
+ TCGv temp_rs = tcg_const_i32(rs);
+ op2 = MASK_SHLL_QB(ctx->opcode);
+ switch (op2) {
+ case OPC_SHLL_QB:
+ gen_helper_shll_qb(cpu_gpr[rd], cpu_env,
+ temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_QB:
+ gen_helper_shllv_qb(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHLL_PH:
+ gen_helper_shll_ph(cpu_gpr[rd], cpu_env,
+ temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_PH:
+ gen_helper_shllv_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHLL_S_PH:
+ gen_helper_shll_s_ph(cpu_gpr[rd], cpu_env,
+ temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_S_PH:
+ gen_helper_shllv_s_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHLL_S_W:
+ gen_helper_shll_s_w(cpu_gpr[rd], cpu_env,
+ temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHLLV_S_W:
+ gen_helper_shllv_s_w(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHRL_QB:
+ gen_helper_shrl_qb(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRLV_QB:
+ gen_helper_shrlv_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHRL_PH:
+ gen_helper_shrl_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRLV_PH:
+ gen_helper_shrlv_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_QB:
+ gen_helper_shra_qb(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_R_QB:
+ gen_helper_shra_r_qb(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_QB:
+ gen_helper_shrav_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_R_QB:
+ gen_helper_shrav_r_qb(cpu_gpr[rd], cpu_gpr[rs],
+ cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_PH:
+ gen_helper_shra_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_R_PH:
+ gen_helper_shra_r_ph(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_PH:
+ gen_helper_shrav_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_R_PH:
+ gen_helper_shrav_r_ph(cpu_gpr[rd], cpu_gpr[rs],
+ cpu_gpr[rt]);
+ break;
+ case OPC_SHRA_R_W:
+ gen_helper_shra_r_w(cpu_gpr[rd], temp_rs, cpu_gpr[rt]);
+ break;
+ case OPC_SHRAV_R_W:
+ gen_helper_shrav_r_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ }
+ tcg_temp_free(temp_rs);
+ break;
+ }
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
Add MIPS DSP GPR-Based Shift instructions Support. Signed-off-by: Jia Liu <proljc@gmail.com> --- target-mips/dsp_helper.c | 411 ++++++++++++++++++++++++++++++++++++++++++++++ target-mips/helper.h | 24 +++ target-mips/translate.c | 114 +++++++++++++ 3 files changed, 549 insertions(+), 0 deletions(-)