From patchwork Sun Mar 25 22:27:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148603 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 47AC3B6EEE for ; Mon, 26 Mar 2012 10:09:17 +1100 (EST) Received: from localhost ([::1]:33890 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBvwj-00063h-D2 for incoming@patchwork.ozlabs.org; Sun, 25 Mar 2012 18:29:57 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBvvl-0003xT-Do for qemu-devel@nongnu.org; Sun, 25 Mar 2012 18:28:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SBvvj-0007xf-I8 for qemu-devel@nongnu.org; Sun, 25 Mar 2012 18:28:56 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:34267) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBvvj-0007uF-9r for qemu-devel@nongnu.org; Sun, 25 Mar 2012 18:28:55 -0400 Received: by mail-pb0-f45.google.com with SMTP id uo5so6347893pbc.4 for ; Sun, 25 Mar 2012 15:28:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=cujPOogphZ/agwoaL5OKEvnz5WmgvP1DnOBvNe7z/Jo=; b=0xJi5dBltd/HinKQ+gSawpBAFZ5jzUvoV/e3KaUTYYYC8Kn50V8XhhhYTHJOGglGuy MtbgCthCI+qh+fee0cAMxTTe33//rvJlZwJvvRMVM1zu+rv6fq2DkCoHTuR70QHZ9hVJ iDIkNy2bKnVFxnnQXj2qYwD3P9yNbss3cDcE4Dcuho5SAltW44nZFCq+1IUKQM0AyQ8M gzTHWgW3sM5BCVhKTyjDve7N3xKYuEqv+Wv1Z8nK1RbVBvQ0Ploo5cYGVKpCLyLzW/MJ irEgh8PYhn+VH2KtBKNDURFsM2i8l9Snni+W06hUOL9tZxCEYAirdbTti1ydcKwUz27u N3Aw== Received: by 10.68.220.65 with SMTP id pu1mr44049626pbc.32.1332714534473; Sun, 25 Mar 2012 15:28:54 -0700 (PDT) Received: from pebble.com ([173.160.232.49]) by mx.google.com with ESMTPS id l4sm11018797pbl.27.2012.03.25.15.28.53 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 25 Mar 2012 15:28:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 25 Mar 2012 15:27:54 -0700 Message-Id: <1332714477-30079-13-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1332714477-30079-1-git-send-email-rth@twiddle.net> References: <1332714477-30079-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 12/15] tcg-sparc: Mask shift immediates to avoid illegal insns. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index c1d5ab1..181ba26 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1184,13 +1184,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, goto gen_arith; case INDEX_op_shl_i32: c = SHIFT_SLL; - goto gen_arith; + do_shift32: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c); + break; case INDEX_op_shr_i32: c = SHIFT_SRL; - goto gen_arith; + goto do_shift32; case INDEX_op_sar_i32: c = SHIFT_SRA; - goto gen_arith; + goto do_shift32; case INDEX_op_mul_i32: c = ARITH_UMUL; goto gen_arith; @@ -1311,13 +1314,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_shl_i64: c = SHIFT_SLLX; - goto gen_arith; + do_shift64: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c); + break; case INDEX_op_shr_i64: c = SHIFT_SRLX; - goto gen_arith; + goto do_shift64; case INDEX_op_sar_i64: c = SHIFT_SRAX; - goto gen_arith; + goto do_shift64; case INDEX_op_mul_i64: c = ARITH_MULX; goto gen_arith;