From patchwork Sat Mar 24 19:01:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 148539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E8D14B6FBA for ; Sun, 25 Mar 2012 06:02:01 +1100 (EST) Received: from localhost ([::1]:45810 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBWDv-0003el-Ri for incoming@patchwork.ozlabs.org; Sat, 24 Mar 2012 15:01:59 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51432) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBWDl-0003ec-IE for qemu-devel@nongnu.org; Sat, 24 Mar 2012 15:01:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SBWDi-0005fc-BX for qemu-devel@nongnu.org; Sat, 24 Mar 2012 15:01:49 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:60098) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBWDi-0005MT-34 for qemu-devel@nongnu.org; Sat, 24 Mar 2012 15:01:46 -0400 Received: by mail-iy0-f173.google.com with SMTP id j26so7402813iaf.4 for ; Sat, 24 Mar 2012 12:01:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:from:date:message-id:subject:to:content-type; bh=1QMYHEqXw7PXEDsDUqOjErjbgfd893tXNxw3ciTshH0=; b=F0F2W4t3UvQsOcbr9ldZd8X0XXXTrGblW+Cy6zfWAkwQY8im4fYgd44eCxuFs7Xw0d tGIgB55g13opoiAQ7zrCT6rlBNGR0yQM4GvTSjksWJr7bD2Z6yExJJ9etyyZ/8AtYvU1 QU0psW8X5kM2Pc0PX9gja709opedAAl9DywCEawD1aOAizwSwWu9bnV/f8hap9QS4J4v rC3yhXVXiTGmYo0IrOOBcVQgYDSxjYyl/PrRZ4/VHbfhixiwOrv1FoerZh3nKyV7bsXY ajmcYwCF4xzyE8YMLTUbu+w8tqRFi1zIylzH/To0HuL+HeEmTzXEWF2BXq+TkLRNt7lT NnSA== Received: by 10.50.47.162 with SMTP id e2mr2093001ign.0.1332615705267; Sat, 24 Mar 2012 12:01:45 -0700 (PDT) MIME-Version: 1.0 Received: by 10.50.75.41 with HTTP; Sat, 24 Mar 2012 12:01:24 -0700 (PDT) From: Blue Swirl Date: Sat, 24 Mar 2012 19:01:24 +0000 Message-ID: To: qemu-devel , Paul Brook , Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.173 Subject: [Qemu-devel] [PATCH 6/6] arm: move load and store helpers, switch to AREG0 free mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add an explicit CPUARMState parameter instead of relying on AREG0 and move load and store helpers to helper.c. Remove AREG0 swapping in tlb_fill(). Remove now empty op_helper.c. Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation and interrupt handling. Reviewed-by: Richard Henderson Signed-off-by: Blue Swirl --- Makefile.target | 6 +--- configure | 2 +- target-arm/helper.c | 54 +++++++++++++++++++++++++++++++++--- target-arm/op_helper.c | 71 ------------------------------------------------ target-arm/translate.c | 6 ++-- 5 files changed, 56 insertions(+), 83 deletions(-) delete mode 100644 target-arm/op_helper.c /* M variants do not implement ARM mode. */ @@ -8133,7 +8133,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw /* Fall through to 32-bit decode. */ } - insn = lduw_code(s->pc); + insn = cpu_lduw_code(env, s->pc); s->pc += 2; insn |= (uint32_t)insn_hw1 << 16; @@ -9163,7 +9163,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) } } - insn = lduw_code(s->pc); + insn = cpu_lduw_code(env, s->pc); s->pc += 2; switch (insn >> 12) { diff --git a/Makefile.target b/Makefile.target index 44b2e83..aa53e28 100644 --- a/Makefile.target +++ b/Makefile.target @@ -80,11 +80,9 @@ libobj-y = exec.o translate-all.o cpu-exec.o translate.o libobj-y += tcg/tcg.o tcg/optimize.o libobj-$(CONFIG_TCG_INTERPRETER) += tci.o libobj-y += fpu/softfloat.o -ifneq ($(TARGET_BASE_ARCH), sparc) -ifneq ($(TARGET_BASE_ARCH), alpha) +ifndef CONFIG_TCG_PASS_AREG0 libobj-y += op_helper.o endif -endif libobj-y += helper.o ifeq ($(TARGET_BASE_ARCH), i386) libobj-y += cpuid.o @@ -109,7 +107,7 @@ $(libobj-y): $(GENERATED_HEADERS) # HELPER_CFLAGS is used for all the legacy code compiled with static register # variables -ifneq ($(TARGET_BASE_ARCH), sparc) +ifndef CONFIG_TCG_PASS_AREG0 op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) endif user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS) diff --git a/configure b/configure index 14ef738..80ca430 100755 --- a/configure +++ b/configure @@ -3608,7 +3608,7 @@ case "$target_arch2" in esac case "$target_arch2" in - alpha | sparc*) + alpha | arm* | sparc*) echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak ;; esac diff --git a/target-arm/helper.c b/target-arm/helper.c index fbf1eea..d54b1d1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -7,6 +7,26 @@ #endif #include "sysemu.h" +#if !defined(CONFIG_USER_ONLY) + +#include "softmmu_exec.h" + +#define MMUSUFFIX _mmu + +#define SHIFT 0 +#include "softmmu_template.h" + +#define SHIFT 1 +#include "softmmu_template.h" + +#define SHIFT 2 +#include "softmmu_template.h" + +#define SHIFT 3 +#include "softmmu_template.h" + +#endif + #define SIGNBIT (uint32_t)0x80000000 static uint32_t cortexa15_cp15_c0_c1[8] = { @@ -1001,7 +1021,7 @@ static void do_interrupt_v7m(CPUARMState *env) case EXCP_BKPT: if (semihosting_enabled) { int nr; - nr = lduw_code(env->regs[15]) & 0xff; + nr = cpu_lduw_code(env, env->regs[15]) & 0xff; if (nr == 0xab) { env->regs[15] += 2; env->regs[0] = do_arm_semihosting(env); @@ -1073,9 +1093,9 @@ void do_interrupt(CPUARMState *env) if (semihosting_enabled) { /* Check for semihosting interrupt. */ if (env->thumb) { - mask = lduw_code(env->regs[15] - 2) & 0xff; + mask = cpu_lduw_code(env, env->regs[15] - 2) & 0xff; } else { - mask = ldl_code(env->regs[15] - 4) & 0xffffff; + mask = cpu_ldl_code(env, env->regs[15] - 4) & 0xffffff; } /* Only intercept calls from privileged modes, to provide some semblance of security. */ @@ -1095,7 +1115,7 @@ void do_interrupt(CPUARMState *env) case EXCP_BKPT: /* See if this is a semihosting syscall. */ if (env->thumb && semihosting_enabled) { - mask = lduw_code(env->regs[15]) & 0xff; + mask = cpu_lduw_code(env, env->regs[15]) & 0xff; if (mask == 0xab && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { env->regs[15] += 2; @@ -1542,6 +1562,32 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, return 1; } +/* try to fill the TLB and return an exception if error. If retaddr is + NULL, it means that the function was called in C code (i.e. not + from generated code or from helper.c) */ +void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, + void *retaddr) +{ + TranslationBlock *tb; + unsigned long pc; + int ret; + + ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx); + if (unlikely(ret)) { + if (retaddr) { + /* now we have a real cpu fault */ + pc = (unsigned long)retaddr; + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc); + } + } + helper_exception(env, env->exception_index); + } +} + target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr) { uint32_t phys_addr; diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c deleted file mode 100644 index f1933c3..0000000 --- a/target-arm/op_helper.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * ARM helper routines - * - * Copyright (c) 2005-2007 CodeSourcery, LLC - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "cpu.h" -#include "dyngen-exec.h" -#include "helper.h" - -#if !defined(CONFIG_USER_ONLY) - -#include "softmmu_exec.h" - -#define MMUSUFFIX _mmu - -#define SHIFT 0 -#include "softmmu_template.h" - -#define SHIFT 1 -#include "softmmu_template.h" - -#define SHIFT 2 -#include "softmmu_template.h" - -#define SHIFT 3 -#include "softmmu_template.h" - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx, - void *retaddr) -{ - TranslationBlock *tb; - CPUARMState *saved_env; - unsigned long pc; - int ret; - - saved_env = env; - env = env1; - ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - pc = (unsigned long)retaddr; - tb = tb_find_pc(pc); - if (tb) { - /* the PC is inside the translated code. It means that we have - a virtual CPU fault */ - cpu_restore_state(tb, env, pc); - } - } - helper_exception(env, env->exception_index); - } - env = saved_env; -} -#endif diff --git a/target-arm/translate.c b/target-arm/translate.c index a3b3449..6535160 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6705,7 +6705,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) TCGv addr; TCGv_i64 tmp64; - insn = ldl_code(s->pc); + insn = cpu_ldl_code(env, s->pc); s->pc += 4;