From patchwork Sat Mar 24 16:51:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148519 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EB88BB6ED0 for ; Sun, 25 Mar 2012 03:53:11 +1100 (EST) Received: from localhost ([::1]:46115 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBUDF-00008g-Sb for incoming@patchwork.ozlabs.org; Sat, 24 Mar 2012 12:53:09 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBUBl-0004mt-Hf for qemu-devel@nongnu.org; Sat, 24 Mar 2012 12:51:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SBUBg-00056c-SN for qemu-devel@nongnu.org; Sat, 24 Mar 2012 12:51:37 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:51044) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBUBg-00054b-Js for qemu-devel@nongnu.org; Sat, 24 Mar 2012 12:51:32 -0400 Received: by mail-pb0-f45.google.com with SMTP id uo5so4534836pbc.4 for ; Sat, 24 Mar 2012 09:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=eSSIux1sHieuf9xWaI90GmEtRJesEfTt1/uY56F5h+A=; b=YPlamxmpI46OdnWd+3ZVdzd3EfyVC6yr42q4aNi9xfiwHqhzIsSa/z/R4XO4DxRwmZ Jo0+FbexAjdZNqUeA4ppfbSBarHoLNe8ORX8bKE3pqTIY37oR7/BwA35Tqe4deyp6DRN KeVF5XRu/KGCzUL1OSaWW4xVHTUPS4j8fMYN0iYH/JAoDenbButKct7DwLhe+9MkDCPq RAkfTCvYACD/0BAsOg6viBFx2zozYEaaOjHLm4W07egw0fmVnbLpcpH9r3Fp+xbno+Km EeWpEddo6FrEifI5bbBwfXpsqkGs2KOcoaEWpUrBktwjE5eXbNxrt+lk8q/M6HoLnoCc /rEg== Received: by 10.68.223.42 with SMTP id qr10mr38822378pbc.127.1332607891675; Sat, 24 Mar 2012 09:51:31 -0700 (PDT) Received: from pebble.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id q8sm8412101pbi.1.2012.03.24.09.51.30 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 24 Mar 2012 09:51:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 Mar 2012 09:51:13 -0700 Message-Id: <1332607875-18895-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1332607875-18895-1-git-send-email-rth@twiddle.net> References: <1332607875-18895-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 08/10] target-alpha: Move memory helpers to mem_helper.c. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This completes the transition away from AREG0. This patch must be last because it requires CONFIG_TCG_PASS_AREG0 set too. Signed-off-by: Richard Henderson --- Makefile.target | 4 +- configure | 2 +- target-alpha/helper.h | 8 +- target-alpha/mem_helper.c | 151 +++++++++++++++++++++++++++++++++++++++++ target-alpha/op_helper.c | 162 --------------------------------------------- target-alpha/translate.c | 10 ++-- 6 files changed, 164 insertions(+), 173 deletions(-) create mode 100644 target-alpha/mem_helper.c delete mode 100644 target-alpha/op_helper.c diff --git a/Makefile.target b/Makefile.target index 254a9fa..44b2e83 100644 --- a/Makefile.target +++ b/Makefile.target @@ -81,8 +81,10 @@ libobj-y += tcg/tcg.o tcg/optimize.o libobj-$(CONFIG_TCG_INTERPRETER) += tci.o libobj-y += fpu/softfloat.o ifneq ($(TARGET_BASE_ARCH), sparc) +ifneq ($(TARGET_BASE_ARCH), alpha) libobj-y += op_helper.o endif +endif libobj-y += helper.o ifeq ($(TARGET_BASE_ARCH), i386) libobj-y += cpuid.o @@ -96,7 +98,7 @@ libobj-y += cpu_init.o endif libobj-$(TARGET_SPARC) += int32_helper.o libobj-$(TARGET_SPARC64) += int64_helper.o -libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o +libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o libobj-y += disas.o libobj-$(CONFIG_TCI_DIS) += tci-dis.o diff --git a/configure b/configure index 8b4e3c1..14ef738 100755 --- a/configure +++ b/configure @@ -3608,7 +3608,7 @@ case "$target_arch2" in esac case "$target_arch2" in - sparc*) + alpha | sparc*) echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak ;; esac diff --git a/target-alpha/helper.h b/target-alpha/helper.h index f057ecf..03cc185 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -104,12 +104,12 @@ DEF_HELPER_2(hw_ret, void, env, i64) DEF_HELPER_1(ldl_phys, i64, i64) DEF_HELPER_1(ldq_phys, i64, i64) -DEF_HELPER_1(ldl_l_phys, i64, i64) -DEF_HELPER_1(ldq_l_phys, i64, i64) +DEF_HELPER_2(ldl_l_phys, i64, env, i64) +DEF_HELPER_2(ldq_l_phys, i64, env, i64) DEF_HELPER_2(stl_phys, void, i64, i64) DEF_HELPER_2(stq_phys, void, i64, i64) -DEF_HELPER_2(stl_c_phys, i64, i64, i64) -DEF_HELPER_2(stq_c_phys, i64, i64, i64) +DEF_HELPER_3(stl_c_phys, i64, env, i64, i64) +DEF_HELPER_3(stq_c_phys, i64, env, i64, i64) DEF_HELPER_FLAGS_1(tbia, TCG_CALL_CONST, void, env) DEF_HELPER_FLAGS_2(tbis, TCG_CALL_CONST, void, env, i64) diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c new file mode 100644 index 0000000..dd5ca49 --- /dev/null +++ b/target-alpha/mem_helper.c @@ -0,0 +1,151 @@ +/* + * Helpers for loads and stores + * + * Copyright (c) 2007 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "cpu.h" +#include "helper.h" + + +/* Softmmu support */ +#ifndef CONFIG_USER_ONLY + +uint64_t helper_ldl_phys(uint64_t p) +{ + return (int32_t)ldl_phys(p); +} + +uint64_t helper_ldq_phys(uint64_t p) +{ + return ldq_phys(p); +} + +uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p) +{ + env->lock_addr = p; + return env->lock_value = (int32_t)ldl_phys(p); +} + +uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p) +{ + env->lock_addr = p; + return env->lock_value = ldq_phys(p); +} + +void helper_stl_phys(uint64_t p, uint64_t v) +{ + stl_phys(p, v); +} + +void helper_stq_phys(uint64_t p, uint64_t v) +{ + stq_phys(p, v); +} + +uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) +{ + uint64_t ret = 0; + + if (p == env->lock_addr) { + int32_t old = ldl_phys(p); + if (old == (int32_t)env->lock_value) { + stl_phys(p, v); + ret = 1; + } + } + env->lock_addr = -1; + + return ret; +} + +uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) +{ + uint64_t ret = 0; + + if (p == env->lock_addr) { + uint64_t old = ldq_phys(p); + if (old == env->lock_value) { + stq_phys(p, v); + ret = 1; + } + } + env->lock_addr = -1; + + return ret; +} + +static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, + int is_write, int is_user, void *retaddr) +{ + uint64_t pc; + uint32_t insn; + + do_restore_state(env, retaddr); + + pc = env->pc; + insn = cpu_ldl_code(env, pc); + + env->trap_arg0 = addr; + env->trap_arg1 = insn >> 26; /* opcode */ + env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ + env->exception_index = EXCP_UNALIGN; + env->error_code = 0; + cpu_loop_exit(env); +} + +void cpu_unassigned_access(CPUAlphaState *env, target_phys_addr_t addr, + int is_write, int is_exec, int unused, int size) +{ + env->trap_arg0 = addr; + env->trap_arg1 = is_write; + dynamic_excp(env, NULL, EXCP_MCHK, 0); +} + +#include "softmmu_exec.h" + +#define MMUSUFFIX _mmu +#define ALIGNED_ONLY + +#define SHIFT 0 +#include "softmmu_template.h" + +#define SHIFT 1 +#include "softmmu_template.h" + +#define SHIFT 2 +#include "softmmu_template.h" + +#define SHIFT 3 +#include "softmmu_template.h" + +/* try to fill the TLB and return an exception if error. If retaddr is + NULL, it means that the function was called in C code (i.e. not + from generated code or from helper.c) */ +/* XXX: fix it to restore all registers */ +void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write, + int mmu_idx, void *retaddr) +{ + int ret; + + ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx); + if (unlikely(ret != 0)) { + do_restore_state(env, retaddr); + /* Exception index and error code are already set */ + cpu_loop_exit(env); + } +} +#endif /* CONFIG_USER_ONLY */ diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c deleted file mode 100644 index df1f01c..0000000 --- a/target-alpha/op_helper.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Alpha emulation cpu micro-operations helpers for qemu. - * - * Copyright (c) 2007 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "cpu.h" -#include "dyngen-exec.h" -#include "host-utils.h" -#include "softfloat.h" -#include "helper.h" -#include "sysemu.h" -#include "qemu-timer.h" - - -/*****************************************************************************/ -/* Softmmu support */ -#if !defined (CONFIG_USER_ONLY) -uint64_t helper_ldl_phys(uint64_t p) -{ - return (int32_t)ldl_phys(p); -} - -uint64_t helper_ldq_phys(uint64_t p) -{ - return ldq_phys(p); -} - -uint64_t helper_ldl_l_phys(uint64_t p) -{ - env->lock_addr = p; - return env->lock_value = (int32_t)ldl_phys(p); -} - -uint64_t helper_ldq_l_phys(uint64_t p) -{ - env->lock_addr = p; - return env->lock_value = ldl_phys(p); -} - -void helper_stl_phys(uint64_t p, uint64_t v) -{ - stl_phys(p, v); -} - -void helper_stq_phys(uint64_t p, uint64_t v) -{ - stq_phys(p, v); -} - -uint64_t helper_stl_c_phys(uint64_t p, uint64_t v) -{ - uint64_t ret = 0; - - if (p == env->lock_addr) { - int32_t old = ldl_phys(p); - if (old == (int32_t)env->lock_value) { - stl_phys(p, v); - ret = 1; - } - } - env->lock_addr = -1; - - return ret; -} - -uint64_t helper_stq_c_phys(uint64_t p, uint64_t v) -{ - uint64_t ret = 0; - - if (p == env->lock_addr) { - uint64_t old = ldq_phys(p); - if (old == env->lock_value) { - stq_phys(p, v); - ret = 1; - } - } - env->lock_addr = -1; - - return ret; -} - -static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, - int is_user, void *retaddr) -{ - uint64_t pc; - uint32_t insn; - - do_restore_state(env, retaddr); - - pc = env->pc; - insn = ldl_code(pc); - - env->trap_arg0 = addr; - env->trap_arg1 = insn >> 26; /* opcode */ - env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ - env->exception_index = EXCP_UNALIGN; - env->error_code = 0; - cpu_loop_exit(env); -} - -void QEMU_NORETURN cpu_unassigned_access(CPUAlphaState *env1, - target_phys_addr_t addr, int is_write, - int is_exec, int unused, int size) -{ - env = env1; - env->trap_arg0 = addr; - env->trap_arg1 = is_write; - dynamic_excp(env1, GETPC(), EXCP_MCHK, 0); -} - -#include "softmmu_exec.h" - -#define MMUSUFFIX _mmu -#define ALIGNED_ONLY - -#define SHIFT 0 -#include "softmmu_template.h" - -#define SHIFT 1 -#include "softmmu_template.h" - -#define SHIFT 2 -#include "softmmu_template.h" - -#define SHIFT 3 -#include "softmmu_template.h" - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUAlphaState *env1, target_ulong addr, int is_write, int mmu_idx, - void *retaddr) -{ - CPUAlphaState *saved_env; - int ret; - - saved_env = env; - env = env1; - ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx); - if (unlikely(ret != 0)) { - do_restore_state(env, retaddr); - /* Exception index and error code are already set */ - cpu_loop_exit(env); - } - env = saved_env; -} -#endif diff --git a/target-alpha/translate.c b/target-alpha/translate.c index cc87320..dd09ad8 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2867,11 +2867,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) break; case 0x2: /* Longword physical access with lock (hw_ldl_l/p) */ - gen_helper_ldl_l_phys(cpu_ir[ra], addr); + gen_helper_ldl_l_phys(cpu_ir[ra], cpu_env, addr); break; case 0x3: /* Quadword physical access with lock (hw_ldq_l/p) */ - gen_helper_ldq_l_phys(cpu_ir[ra], addr); + gen_helper_ldq_l_phys(cpu_ir[ra], cpu_env, addr); break; case 0x4: /* Longword virtual PTE fetch (hw_ldl/v) */ @@ -3180,11 +3180,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) break; case 0x2: /* Longword physical access with lock */ - gen_helper_stl_c_phys(val, addr, val); + gen_helper_stl_c_phys(val, cpu_env, addr, val); break; case 0x3: /* Quadword physical access with lock */ - gen_helper_stq_c_phys(val, addr, val); + gen_helper_stq_c_phys(val, cpu_env, addr, val); break; case 0x4: /* Longword virtual access */ @@ -3420,7 +3420,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); - insn = ldl_code(ctx.pc); + insn = cpu_ldl_code(env, ctx.pc); num_insns++; if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {