From patchwork Fri Mar 23 16:24:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 148470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CA0D8B6EF1 for ; Sat, 24 Mar 2012 03:25:04 +1100 (EST) Received: from localhost ([::1]:60944 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SB7IU-0006dx-Ks for incoming@patchwork.ozlabs.org; Fri, 23 Mar 2012 12:25:02 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51360) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SB7IF-0006QF-Nf for qemu-devel@nongnu.org; Fri, 23 Mar 2012 12:24:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SB7I7-0007om-5l for qemu-devel@nongnu.org; Fri, 23 Mar 2012 12:24:47 -0400 Received: from cantor2.suse.de ([195.135.220.15]:33803 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SB7I6-0007oX-S3 for qemu-devel@nongnu.org; Fri, 23 Mar 2012 12:24:39 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id AEAD989994; Fri, 23 Mar 2012 17:24:37 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Fri, 23 Mar 2012 17:24:34 +0100 Message-Id: <1332519874-15929-3-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1332519874-15929-1-git-send-email-afaerber@suse.de> References: <1332519874-15929-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [PATCH v5 2/2] target-arm: Minimalistic CPU QOM'ification X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce only one non-abstract type TYPE_ARM_CPU and do not touch cp15 registers to not interfere with Peter's ongoing remodelling. Embed CPUARMState as first (additional) field of ARMCPU. Signed-off-by: Andreas Färber Reviewed-by: Peter Maydell --- Makefile.target | 1 + target-arm/cpu-qom.h | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ target-arm/cpu.c | 37 +++++++++++++++++++++++++++ target-arm/cpu.h | 1 + target-arm/helper.c | 4 ++- 5 files changed, 110 insertions(+), 1 deletions(-) create mode 100644 target-arm/cpu-qom.h create mode 100644 target-arm/cpu.c diff --git a/Makefile.target b/Makefile.target index 63cf769..4fa03e4 100644 --- a/Makefile.target +++ b/Makefile.target @@ -90,6 +90,7 @@ endif libobj-$(TARGET_SPARC64) += vis_helper.o libobj-$(CONFIG_NEED_MMU) += mmu.o libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o +libobj-$(TARGET_ARM) += cpu.o ifeq ($(TARGET_BASE_ARCH), sparc) libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o libobj-y += cpu_init.o diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h new file mode 100644 index 0000000..464a29b --- /dev/null +++ b/target-arm/cpu-qom.h @@ -0,0 +1,68 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ +#ifndef QEMU_ARM_CPU_QOM_H +#define QEMU_ARM_CPU_QOM_H + +#include "qemu/cpu.h" +#include "cpu.h" + +#define TYPE_ARM_CPU "arm-cpu" + +#define ARM_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU) +#define ARM_CPU(obj) \ + OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU) +#define ARM_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) + +/** + * ARMCPUClass: + * + * An ARM CPU model. + */ +typedef struct ARMCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ +} ARMCPUClass; + +/** + * ARMCPU: + * @env: #CPUARMState + * + * An ARM CPU core. + */ +typedef struct ARMCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUARMState env; +} ARMCPU; + +static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) +{ + return ARM_CPU(container_of(env, ARMCPU, env)); +} + +#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) + + +#endif diff --git a/target-arm/cpu.c b/target-arm/cpu.c new file mode 100644 index 0000000..8019be0 --- /dev/null +++ b/target-arm/cpu.c @@ -0,0 +1,37 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "cpu-qom.h" +#include "qemu-common.h" + +static const TypeInfo arm_cpu_type_info = { + .name = TYPE_ARM_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(ARMCPU), + .abstract = false, /* TODO Reconsider once cp15 reworked. */ + .class_size = sizeof(ARMCPUClass), +}; + +static void arm_cpu_register_types(void) +{ + type_register_static(&arm_cpu_type_info); +} + +type_init(arm_cpu_register_types) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 69ef142..a68df61 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -475,6 +475,7 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) #endif #include "cpu-all.h" +#include "cpu-qom.h" /* Bit usage in the TB flags field: */ #define ARM_TBFLAG_THUMB_SHIFT 0 diff --git a/target-arm/helper.c b/target-arm/helper.c index 1ce8105..709de52 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -400,6 +400,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) CPUARMState *cpu_arm_init(const char *cpu_model) { + ARMCPU *cpu; CPUARMState *env; uint32_t id; static int inited = 0; @@ -407,7 +408,8 @@ CPUARMState *cpu_arm_init(const char *cpu_model) id = cpu_arm_find_by_name(cpu_model); if (id == 0) return NULL; - env = g_malloc0(sizeof(CPUARMState)); + cpu = ARM_CPU(object_new(TYPE_ARM_CPU)); + env = &cpu->env; cpu_exec_init(env); if (tcg_enabled() && !inited) { inited = 1;