| Message ID | 1332493721-28309-10-git-send-email-peppe.cavallaro@st.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
> -----Original Message----- > From: netdev-owner@vger.kernel.org > [mailto:netdev-owner@vger.kernel.org] On Behalf Of Giuseppe CAVALLARO > Sent: 23 March 2012 09:09 > To: netdev@vger.kernel.org > Cc: davem@davemloft.net; srinivas.kandagatla@st.com; > deepak.sikri@st.com; spear-devel@list.st.com; > shiraz.hashim@st.com; viresh.kumar@st.com; > bhutchings@solarflare.com; Giuseppe Cavallaro > Subject: [PATCH 09/10] stmmac: MDC clock dynamically based on > the csr clock input > > If a specific clk_csr value is passed from the platform > this means that the CSR Clock Range selection cannot be > changed at run-time and it is fixed (as reported in the driver > documentation). Viceversa the driver will try to set the MDC > clock dynamically according to the actual clock input. > > Signed-off-by: Deepak Sikri <deepak.sikri@st.com> > Reviewed-by: Francesco Virlinzi <francesco.virlinzi@st.com> > Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> > --- > Documentation/networking/stmmac.txt | 2 +- > drivers/net/ethernet/stmicro/stmmac/common.h | 10 +++++ > drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 40 > +++++++++++++++++++++ > drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 4 +- > 5 files changed, 54 insertions(+), 3 deletions(-) > > diff --git a/Documentation/networking/stmmac.txt > b/Documentation/networking/stmmac.txt > index eacb640..ab1e8d7 100644 > --- a/Documentation/networking/stmmac.txt > +++ b/Documentation/networking/stmmac.txt > @@ -137,7 +137,7 @@ Where: > o pbl: the Programmable Burst Length is maximum number of beats to > be transferred in one DMA transaction. > GMAC also enables the 4xPBL by default. > - o clk_csr: CSR Clock range selection. > + o clk_csr: fixed CSR Clock range selection. > o has_gmac: uses the GMAC core. > o enh_desc: if sets the MAC will use the enhanced > descriptor structure. > o tx_coe: core is able to perform the tx csum in HW. > diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h > b/drivers/net/ethernet/stmicro/stmmac/common.h > index f4df1eb..312e3f1 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/common.h > +++ b/drivers/net/ethernet/stmicro/stmmac/common.h > @@ -97,6 +97,16 @@ struct stmmac_extra_stats { > unsigned long normal_irq_n; > }; > > +/* CSR Frequency Access Defines*/ > +#define CSR_F_35M 35000000 > +#define CSR_F_60M 60000000 > +#define CSR_F_100M 100000000 > +#define CSR_F_150M 150000000 > +#define CSR_F_250M 50000000 > +#define CSR_F_300M 300000000 The value of CSR_F_250M looks like a typo. These defines look rather pointless to me though! Another patch has: > ----------------------------------------- > Selection MDC Clock > ----------------------------------------- > 1000 clk_csr_i/4 > 1001 clk_csr_i/6 > 1010 clk_csr_i/8 > 1011 clk_csr_i/10 > 1100 clk_csr_i/12 > 1101 clk_csr_i/14 > 1110 clk_csr_i/16 > 1111 clk_csr_i/18 I detect a pattern ... David -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 3/23/2012 10:53 AM, David Laight wrote: > > >> -----Original Message----- >> From: netdev-owner@vger.kernel.org >> [mailto:netdev-owner@vger.kernel.org] On Behalf Of Giuseppe CAVALLARO >> Sent: 23 March 2012 09:09 >> To: netdev@vger.kernel.org >> Cc: davem@davemloft.net; srinivas.kandagatla@st.com; >> deepak.sikri@st.com; spear-devel@list.st.com; >> shiraz.hashim@st.com; viresh.kumar@st.com; >> bhutchings@solarflare.com; Giuseppe Cavallaro >> Subject: [PATCH 09/10] stmmac: MDC clock dynamically based on >> the csr clock input >> >> If a specific clk_csr value is passed from the platform >> this means that the CSR Clock Range selection cannot be >> changed at run-time and it is fixed (as reported in the driver >> documentation). Viceversa the driver will try to set the MDC >> clock dynamically according to the actual clock input. >> >> Signed-off-by: Deepak Sikri <deepak.sikri@st.com> >> Reviewed-by: Francesco Virlinzi <francesco.virlinzi@st.com> >> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> >> --- >> Documentation/networking/stmmac.txt | 2 +- >> drivers/net/ethernet/stmicro/stmmac/common.h | 10 +++++ >> drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + >> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 40 >> +++++++++++++++++++++ >> drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 4 +- >> 5 files changed, 54 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/networking/stmmac.txt >> b/Documentation/networking/stmmac.txt >> index eacb640..ab1e8d7 100644 >> --- a/Documentation/networking/stmmac.txt >> +++ b/Documentation/networking/stmmac.txt >> @@ -137,7 +137,7 @@ Where: >> o pbl: the Programmable Burst Length is maximum number of beats to >> be transferred in one DMA transaction. >> GMAC also enables the 4xPBL by default. >> - o clk_csr: CSR Clock range selection. >> + o clk_csr: fixed CSR Clock range selection. >> o has_gmac: uses the GMAC core. >> o enh_desc: if sets the MAC will use the enhanced >> descriptor structure. >> o tx_coe: core is able to perform the tx csum in HW. >> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h >> b/drivers/net/ethernet/stmicro/stmmac/common.h >> index f4df1eb..312e3f1 100644 >> --- a/drivers/net/ethernet/stmicro/stmmac/common.h >> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h >> @@ -97,6 +97,16 @@ struct stmmac_extra_stats { >> unsigned long normal_irq_n; >> }; >> >> +/* CSR Frequency Access Defines*/ >> +#define CSR_F_35M 35000000 >> +#define CSR_F_60M 60000000 >> +#define CSR_F_100M 100000000 >> +#define CSR_F_150M 150000000 >> +#define CSR_F_250M 50000000 >> +#define CSR_F_300M 300000000 > > The value of CSR_F_250M looks like a typo. yes you are right, I'll fix it and re-send the all patches. > These defines look rather pointless to me though! > > Another patch has: >> ----------------------------------------- >> Selection MDC Clock >> ----------------------------------------- >> 1000 clk_csr_i/4 >> 1001 clk_csr_i/6 >> 1010 clk_csr_i/8 >> 1011 clk_csr_i/10 >> 1100 clk_csr_i/12 >> 1101 clk_csr_i/14 >> 1110 clk_csr_i/16 >> 1111 clk_csr_i/18 > I detect a pattern ... On this mac, the MDC clock can be set by user in several ways. if the bit Reg4 bit 5 is 0 so the clock divisor will be driven according to a fixed range of frq (CSR_F_35M & CO). If the bit 5 is set then "custom" divisors can be used. I know it's quite tricky but these patches (from SPEAr) that I reviewed, indeed, added an useful fix to dynamically set the MDC clock according to the actual clock source. This also helped somebody on custom boards. Peppe > > David > > > > -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt index eacb640..ab1e8d7 100644 --- a/Documentation/networking/stmmac.txt +++ b/Documentation/networking/stmmac.txt @@ -137,7 +137,7 @@ Where: o pbl: the Programmable Burst Length is maximum number of beats to be transferred in one DMA transaction. GMAC also enables the 4xPBL by default. - o clk_csr: CSR Clock range selection. + o clk_csr: fixed CSR Clock range selection. o has_gmac: uses the GMAC core. o enh_desc: if sets the MAC will use the enhanced descriptor structure. o tx_coe: core is able to perform the tx csum in HW. diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index f4df1eb..312e3f1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -97,6 +97,16 @@ struct stmmac_extra_stats { unsigned long normal_irq_n; }; +/* CSR Frequency Access Defines*/ +#define CSR_F_35M 35000000 +#define CSR_F_60M 60000000 +#define CSR_F_100M 100000000 +#define CSR_F_150M 150000000 +#define CSR_F_250M 50000000 +#define CSR_F_300M 300000000 + +#define MAC_CSR_H_FRQ_MASK 0x20 + #define HASH_TABLE_SIZE 64 #define PAUSE_TIME 0x200 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index 7182f15..ddd0769 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -84,6 +84,7 @@ struct stmmac_priv { #ifdef CONFIG_HAVE_CLK struct clk *stmmac_clk; #endif + int clk_csr; }; extern int phyaddr; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 08b4d05..c0d83ad 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -163,6 +163,35 @@ static void stmmac_verify_args(void) pause = PAUSE_TIME; } +static void stmmac_clk_csr_set(struct stmmac_priv *priv) +{ +#ifdef CONFIG_HAVE_CLK + u32 clk_rate; + + clk_rate = clk_get_rate(priv->stmmac_clk); + + /* Platform provided default clk_csr would be assumed valid + * for all other cases except for the below mentioned ones. */ + if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { + if (clk_rate < CSR_F_35M) + priv->clk_csr = STMMAC_CSR_20_35M; + else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) + priv->clk_csr = STMMAC_CSR_35_60M; + else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) + priv->clk_csr = STMMAC_CSR_60_100M; + else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) + priv->clk_csr = STMMAC_CSR_100_150M; + else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) + priv->clk_csr = STMMAC_CSR_150_250M; + else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) + priv->clk_csr = STMMAC_CSR_250_300M; + } /* For values higher than the IEEE 802.3 specified frequency + * we can not estimate the proper divider as it is not known + * the frequency of clk_csr_i. So we do not change the default + * divider. */ +#endif +} + #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) static void print_pkt(unsigned char *buf, int len) { @@ -1882,6 +1911,17 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device, if (stmmac_clk_get(priv)) goto error; + /* If a specific clk_csr value is passed from the platform + * this means that the CSR Clock Range selection cannot be + * changed at run-time and it is fixed. Viceversa the driver'll try to + * set the MDC clock dynamically according to the csr actual + * clock input. + */ + if (!priv->plat->clk_csr) + stmmac_clk_csr_set(priv); + else + priv->clk_csr = priv->plat->clk_csr; + return priv; error: diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index 1a42014..ade1082 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -70,7 +70,7 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) int data; u16 regValue = (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))); - regValue |= MII_BUSY | ((priv->plat->clk_csr & 0xF) << 2); + regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) return -EBUSY; @@ -106,7 +106,7 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) | MII_WRITE; - value |= MII_BUSY | ((priv->plat->clk_csr & 0xF) << 2); + value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); /* Wait until any existing MII operation is complete */ if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))