From patchwork Wed Mar 21 04:42:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 147910 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8751CB6EF1 for ; Wed, 21 Mar 2012 15:58:18 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EFFF1280C4; Wed, 21 Mar 2012 05:58:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8riWVFbgGbqs; Wed, 21 Mar 2012 05:58:14 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 98432280B8; Wed, 21 Mar 2012 05:58:13 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A46A3280B8 for ; Wed, 21 Mar 2012 05:58:11 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YUlfA3vwLS1V for ; Wed, 21 Mar 2012 05:58:10 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com [216.32.181.181]) by theia.denx.de (Postfix) with ESMTPS id 79D7E280B6 for ; Wed, 21 Mar 2012 05:58:08 +0100 (CET) Received: from mail9-ch1-R.bigfish.com (10.43.68.243) by CH1EHSOBE003.bigfish.com (10.43.70.53) with Microsoft SMTP Server id 14.1.225.23; Wed, 21 Mar 2012 04:42:53 +0000 Received: from mail9-ch1 (localhost [127.0.0.1]) by mail9-ch1-R.bigfish.com (Postfix) with ESMTP id 8D0811C06D1 for ; Wed, 21 Mar 2012 04:42:53 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839hd24h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail9-ch1 (localhost.localdomain [127.0.0.1]) by mail9-ch1 (MessageSwitch) id 1332304971805750_2309; Wed, 21 Mar 2012 04:42:51 +0000 (UTC) Received: from CH1EHSMHS012.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.231]) by mail9-ch1.bigfish.com (Postfix) with ESMTP id BFA4D1E004C for ; Wed, 21 Mar 2012 04:42:51 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS012.bigfish.com (10.43.70.12) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 21 Mar 2012 04:42:51 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.1.355.3; Tue, 20 Mar 2012 23:42:56 -0500 Received: from b32579-VirtualBox.ap.freescale.net (B32579-02.ap.freescale.net [10.232.132.181]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q2L4gpbP008128; Tue, 20 Mar 2012 21:42:54 -0700 From: Prabhakar Kushwaha To: Date: Wed, 21 Mar 2012 10:12:49 +0530 Message-ID: <1332304969-10800-1-git-send-email-prabhakar@freescale.com> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Marius Grigoras , Catalin Udma , afleming@freescale.com, Radu Lazarescu Subject: [U-Boot] [PATCH 2/4][v2] powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always. Where MSR = Machine State register Make sure of MSR[DE] bit is set uniformaly across the different execution address space i.e. AS0 and AS1. Signed-off-by: Radu Lazarescu Signed-off-by: Catalin Udma Signed-off-by: Marius Grigoras Signed-off-by: Prabhakar Kushwaha --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: - Avoid MSR_DE negation in arch_preboot - Made MSR_DE set code independent of any #define Tested on - SoC having E500 Family processor (P1010RDB, BSC9131RDB) - SoC having E500MC Family processor (P4080DS, P3041DS) arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2e4a06c..3bcbffa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -532,7 +532,7 @@ void arch_preboot_os(void) * disabled by the time we get called. */ msr = mfmsr(); - msr &= ~(MSR_ME|MSR_CE|MSR_DE); + msr &= ~(MSR_ME|MSR_CE); mtmsr(msr); setup_ivors(); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 7bfa2d5..597151b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -82,6 +82,9 @@ .globl _start_e500 _start_e500: +/* Enable debug exception */ + li r1,MSR_DE + mtmsr r1 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) /* ISBC uses L2 as stack. @@ -729,8 +732,8 @@ create_init_ram_area: msync tlbwe - lis r6,MSR_IS|MSR_DS@h - ori r6,r6,MSR_IS|MSR_DS@l + lis r6,MSR_IS|MSR_DS|MSR_DE@h + ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l lis r7,switch_as@h ori r7,r7,switch_as@l