From patchwork Mon Mar 19 21:57:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 147650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 37086B6F6E for ; Tue, 20 Mar 2012 08:57:52 +1100 (EST) Received: from localhost ([::1]:51711 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9kaM-0007PS-4s for incoming@patchwork.ozlabs.org; Mon, 19 Mar 2012 17:57:50 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9kaC-0007Nq-Kv for qemu-devel@nongnu.org; Mon, 19 Mar 2012 17:57:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S9ka9-0005aH-VG for qemu-devel@nongnu.org; Mon, 19 Mar 2012 17:57:40 -0400 Received: from mail-yw0-f45.google.com ([209.85.213.45]:63199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9ka9-0005aA-NM for qemu-devel@nongnu.org; Mon, 19 Mar 2012 17:57:37 -0400 Received: by yhoo21 with SMTP id o21so6899140yho.4 for ; Mon, 19 Mar 2012 14:57:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:from:date:message-id:subject:to:content-type; bh=oaqdL/AY3NuUo0POuAxvUoSX5XLtq86nGApv74F+WXE=; b=OoIrmftHWTOmPAdJ0+xHh/ITEkZrCkLvsgmJi78GCKOZmboXshIbMbea0DR0gB67HV 0R/3vFyFHbT27zG0ZRaWZBRnvUurIrHOw5rMOlRds3PlHSDWxCrfJwMqqN95gvPje3x/ k6c6e1sKslbdl0nWnR5XI938EGqy0i7S1iu78GToBmpGScfYB54XYq/DpthkjqYK7S57 jUXXWgH01gtW92Ezj+phADTu3bli1qCQ3C8h/LqosGUEq9epcyCbBhaQTBzhsVyC46qx Hue54kfkIhSicPvPLuqf72TuZYkGPMNbEVtUb68qDABHvPRNgq3rpwLwDimfitWpTmVM 10NQ== Received: by 10.50.156.135 with SMTP id we7mr7328907igb.0.1332194255371; Mon, 19 Mar 2012 14:57:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.50.75.41 with HTTP; Mon, 19 Mar 2012 14:57:15 -0700 (PDT) From: Blue Swirl Date: Mon, 19 Mar 2012 21:57:15 +0000 Message-ID: To: Paul Brook , Peter Maydell , qemu-devel X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.213.45 Subject: [Qemu-devel] [PATCH 4/6] arm: move cpsr and banked register access to helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add an explicit CPUARMState parameter instead of relying on AREG0 and move cpsr and banked register access to helper.c. Signed-off-by: Blue Swirl --- target-arm/helper.c | 42 ++++++++++++++++++++++++++++++++++++++++++ target-arm/helper.h | 8 ++++---- target-arm/op_helper.c | 42 ------------------------------------------ target-arm/translate.c | 12 ++++++------ 4 files changed, 52 insertions(+), 52 deletions(-) } @@ -7890,7 +7890,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = gen_ld32(addr, IS_USER(s)); if (user) { tmp2 = tcg_const_i32(i); - gen_helper_set_user_reg(tmp2, tmp); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp); } else if (i == rn) { @@ -7909,7 +7909,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) } else if (user) { tmp = tcg_temp_new_i32(); tmp2 = tcg_const_i32(i); - gen_helper_get_user_reg(tmp, tmp2); + gen_helper_get_user_reg(tmp, cpu_env, tmp2); tcg_temp_free_i32(tmp2); } else { tmp = load_reg(s, i); @@ -8282,7 +8282,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw gen_st32(tmp, addr, 0); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp); + gen_helper_cpsr_read(tmp, cpu_env); gen_st32(tmp, addr, 0); if (insn & (1 << 21)) { if ((insn & (1 << 24)) == 0) { @@ -8803,7 +8803,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw gen_helper_v7m_mrs(tmp, cpu_env, addr); tcg_temp_free_i32(addr); } else { - gen_helper_cpsr_read(tmp); + gen_helper_cpsr_read(tmp, cpu_env); } store_reg(s, rd, tmp); break; diff --git a/target-arm/helper.c b/target-arm/helper.c index 3b3d122..77415b3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2549,6 +2549,48 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #endif +uint32_t HELPER(cpsr_read)(CPUARMState *env) +{ + return cpsr_read(env) & ~CPSR_EXEC; +} + +void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) +{ + cpsr_write(env, val, mask); +} + +/* Access to user mode registers from privileged modes. */ +uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) +{ + uint32_t val; + + if (regno == 13) { + val = env->banked_r13[0]; + } else if (regno == 14) { + val = env->banked_r14[0]; + } else if (regno >= 8 + && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { + val = env->usr_regs[regno - 8]; + } else { + val = env->regs[regno]; + } + return val; +} + +void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val) +{ + if (regno == 13) { + env->banked_r13[0] = val; + } else if (regno == 14) { + env->banked_r14[0] = val; + } else if (regno >= 8 + && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { + env->usr_regs[regno - 8] = val; + } else { + env->regs[regno] = val; + } +} + /* Note that signed overflow is undefined in C. The following routines are careful to use unsigned types where modulo arithmetic is required. Failure to do so _will_ break on newer gcc. */ diff --git a/target-arm/helper.h b/target-arm/helper.h index e2ade6f..3e5f92e 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -53,8 +53,8 @@ DEF_HELPER_3(sel_flags, i32, i32, i32, i32) DEF_HELPER_1(exception, void, i32) DEF_HELPER_0(wfi, void) -DEF_HELPER_2(cpsr_write, void, i32, i32) -DEF_HELPER_0(cpsr_read, i32) +DEF_HELPER_3(cpsr_write, void, env, i32, i32) +DEF_HELPER_1(cpsr_read, i32, env) DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) @@ -68,8 +68,8 @@ DEF_HELPER_2(get_cp, i32, env, i32) DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) -DEF_HELPER_1(get_user_reg, i32, i32) -DEF_HELPER_2(set_user_reg, void, i32, i32) +DEF_HELPER_2(get_user_reg, i32, env, i32) +DEF_HELPER_3(set_user_reg, void, env, i32, i32) DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index fc1e7ef..b1ced67 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -90,45 +90,3 @@ void HELPER(exception)(uint32_t excp) env->exception_index = excp; cpu_loop_exit(env); } - -uint32_t HELPER(cpsr_read)(void) -{ - return cpsr_read(env) & ~CPSR_EXEC; -} - -void HELPER(cpsr_write)(uint32_t val, uint32_t mask) -{ - cpsr_write(env, val, mask); -} - -/* Access to user mode registers from privileged modes. */ -uint32_t HELPER(get_user_reg)(uint32_t regno) -{ - uint32_t val; - - if (regno == 13) { - val = env->banked_r13[0]; - } else if (regno == 14) { - val = env->banked_r14[0]; - } else if (regno >= 8 - && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { - val = env->usr_regs[regno - 8]; - } else { - val = env->regs[regno]; - } - return val; -} - -void HELPER(set_user_reg)(uint32_t regno, uint32_t val) -{ - if (regno == 13) { - env->banked_r13[0] = val; - } else if (regno == 14) { - env->banked_r14[0] = val; - } else if (regno >= 8 - && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { - env->usr_regs[regno - 8] = val; - } else { - env->regs[regno] = val; - } -} diff --git a/target-arm/translate.c b/target-arm/translate.c index 0a41dc8..d654255 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -198,7 +198,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) static inline void gen_set_cpsr(TCGv var, uint32_t mask) { TCGv tmp_mask = tcg_const_i32(mask); - gen_helper_cpsr_write(var, tmp_mask); + gen_helper_cpsr_write(cpu_env, var, tmp_mask); tcg_temp_free_i32(tmp_mask); } /* Set NZCV flags from the high 4 bits of var. */ @@ -6989,7 +6989,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = load_cpu_field(spsr); } else { tmp = tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp); + gen_helper_cpsr_read(tmp, cpu_env); } store_reg(s, rd, tmp);