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[2/3] target-arm: Clear IT bits when taking exceptions in v7M

Message ID 1331922106-11774-3-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell March 16, 2012, 6:21 p.m. UTC 
When taking an exception for an M profile core, we must clear
the IT bits. Since the IT bits are cached in env->condexec_bits
we must clear them there: writing the bits in env->uncached_cpsr
has no effect. (Reported as LP:944645.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
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Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4116fee..1314f23 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -877,7 +877,8 @@  static void do_interrupt_v7m(CPUARMState *env)
     v7m_push(env, env->regs[1]);
     v7m_push(env, env->regs[0]);
     switch_v7m_sp(env, 0);
-    env->uncached_cpsr &= ~CPSR_IT;
+    /* Clear IT bits */
+    env->condexec_bits = 0;
     env->regs[14] = lr;
     addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
     env->regs[15] = addr & 0xfffffffe;