From patchwork Thu Mar 15 14:30:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Starikovskiy X-Patchwork-Id: 147029 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0FC2BB6F13 for ; Fri, 16 Mar 2012 01:31:18 +1100 (EST) Received: from localhost ([::1]:53225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S8Bhz-0005EN-Rj for incoming@patchwork.ozlabs.org; Thu, 15 Mar 2012 10:31:15 -0400 Received: from eggs.gnu.org ([208.118.235.92]:38131) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S8BhW-00047q-MX for qemu-devel@nongnu.org; Thu, 15 Mar 2012 10:30:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S8Bh6-0002QT-Jt for qemu-devel@nongnu.org; Thu, 15 Mar 2012 10:30:46 -0400 Received: from nm11.bullet.mail.ukl.yahoo.com ([217.146.183.185]:34268) by eggs.gnu.org with smtp (Exim 4.71) (envelope-from ) id 1S8Bh6-0002Q0-4b for qemu-devel@nongnu.org; Thu, 15 Mar 2012 10:30:20 -0400 Received: from [217.146.183.215] by nm11.bullet.mail.ukl.yahoo.com with NNFMP; 15 Mar 2012 14:30:18 -0000 Received: from [77.238.184.58] by tm8.bullet.mail.ukl.yahoo.com with NNFMP; 15 Mar 2012 14:30:17 -0000 Received: from [127.0.0.1] by smtp127.mail.ukl.yahoo.com with NNFMP; 15 Mar 2012 14:30:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ymail.com; s=s1024; t=1331821817; bh=87e3X5O1wBXO7jK+mSfo30eULfie8gh80ElCvC7nRnw=; h=X-Yahoo-Newman-Id:X-Yahoo-Newman-Property:X-YMail-OSG:X-Yahoo-SMTP:Received:Subject:To:From:Date:Message-ID:User-Agent:MIME-Version:Content-Type:Content-Transfer-Encoding; b=k24LSDV5NwN4Bf0BHgacJVSavBtxMdrdEv+RjZqM6/OdUpjdxr4b3m+CVdjILxaWy1bfm0vvbKTJjfDd3oJOw1Yz8Bi6XlXXEL+qte8JY0MvIRPYo0KwcAk9MYxCJa5jszqoEJb9//PCR1YV2FuOGZ1X/YZjQOKAKvoHFn7Igi0= X-Yahoo-Newman-Id: 901456.15896.bm@smtp127.mail.ukl.yahoo.com X-Yahoo-Newman-Property: ymail-3 X-YMail-OSG: E6NdHmYVM1n5cV7.YBT2gYrUh8.hgqDHU7i0B0wgxWIt6uB Xkvq8fC6nFaFD4g6BC5WdcaX0Y_VRGpkKysNU_46qRIp35auk9aa7TddiSt6 18cQ7L8BpeiWzxTijBTjMf2psUf32BNqPHA9PP46C8RK1BJMUACaXbzc1Y1K FxYK8R3NCvXBuFEON3jbWKscqTKjNdHFaU0NFfidVdRHpbtrhLQKVLqpRZiL 4tmqQ4e_Qkv0IyzmpOfHDoq2vj.5cH3flYMYM67ihmi5kbfCaQ6l2eCm_HZ9 piHmGcofvxZZEnIJlMv.W44RQVaNChV5U4dAwkKG_32WV7_XuZzfduPBh2c2 UrGUgH9ZzlJ8dGSLwyoxxKwpmTaO17Ie4w_vV14g65BPsarLgYI5SoFPB6A5 qMWthLuyMAsO_YZX3u8XKF6vzWA7jjeJg4w-- X-Yahoo-SMTP: RQd6UNeswBCQ2fC9eaSG0twUs6zySTuXUlUG9HuS_w-- Received: from localhost (aystarik@80.251.228.149 with plain) by smtp127.mail.ukl.yahoo.com with SMTP; 15 Mar 2012 14:30:17 +0000 GMT To: qemu-devel@nongnu.org From: Alexey Starikovskiy Date: Thu, 15 Mar 2012 18:30:15 +0400 Message-ID: <20120315143015.6381.14579.stgit@x201> User-Agent: StGit/0.15 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.146.183.185 Subject: [Qemu-devel] [PATCH v4 1/3] Add support for 64bit ARM system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Alexey Starikovskiy --- target-arm/cpu.h | 10 ++++------ target-arm/helper.c | 14 +++++++------- target-arm/machine.c | 16 ++++++---------- 3 files changed, 17 insertions(+), 23 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 26c114b..a0cdde3 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -117,11 +117,9 @@ typedef struct CPUARMState { uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ - uint32_t c2_base0; /* MMU translation table base 0. */ - uint32_t c2_base1; /* MMU translation table base 1. */ + uint64_t c2_base0; /* MMU translation table base 0. */ + uint64_t c2_base1; /* MMU translation table base 1. */ uint32_t c2_control; /* MMU translation table base control. */ - uint32_t c2_mask; /* MMU translation table base selection mask. */ - uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ uint32_t c3; /* MMU domain access control register @@ -131,7 +129,7 @@ typedef struct CPUARMState { uint32_t c6_region[8]; /* MPU base/size registers. */ uint32_t c6_insn; /* Fault address registers. */ uint32_t c6_data; - uint32_t c7_par; /* Translation result. */ + uint64_t c7_par; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint32_t c9_pmcr; /* performance monitor control register */ @@ -455,7 +453,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 6 +#define CPU_SAVE_VERSION 7 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/helper.c b/target-arm/helper.c index 8a08db8..2e61861 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -325,7 +325,6 @@ void cpu_state_reset(CPUARMState *env) } } env->vfp.xregs[ARM_VFP_FPEXC] = 0; - env->cp15.c2_base_mask = 0xffffc000u; /* v7 performance monitor control register: same implementor * field as main ID register, and we implement no event counters. */ @@ -1050,12 +1049,15 @@ static inline int check_ap(CPUARMState *env, int ap, int domain_prot, static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address) { uint32_t table; + int t0size = env->cp15.c2_control & 0x7; + uint32_t mask = ~(((uint32_t)0xffffffffu) >> t0size); - if (address & env->cp15.c2_mask) + if (address & mask) { table = env->cp15.c2_base1 & 0xffffc000; - else - table = env->cp15.c2_base0 & env->cp15.c2_base_mask; - + } else { + mask = ~((uint32_t)0x3fffu >> t0size); + table = env->cp15.c2_base0 & mask; + } table |= (address >> 18) & 0x3ffc; return table; } @@ -1531,8 +1533,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) case 2: val &= 7; env->cp15.c2_control = val; - env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val); - env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val); break; default: goto bad_reg; diff --git a/target-arm/machine.c b/target-arm/machine.c index f66b8df..8fa738e 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -27,11 +27,9 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->cp15.c1_coproc); qemu_put_be32(f, env->cp15.c1_xscaleauxcr); qemu_put_be32(f, env->cp15.c1_scr); - qemu_put_be32(f, env->cp15.c2_base0); - qemu_put_be32(f, env->cp15.c2_base1); + qemu_put_be64(f, env->cp15.c2_base0); + qemu_put_be64(f, env->cp15.c2_base1); qemu_put_be32(f, env->cp15.c2_control); - qemu_put_be32(f, env->cp15.c2_mask); - qemu_put_be32(f, env->cp15.c2_base_mask); qemu_put_be32(f, env->cp15.c2_data); qemu_put_be32(f, env->cp15.c2_insn); qemu_put_be32(f, env->cp15.c3); @@ -42,7 +40,7 @@ void cpu_save(QEMUFile *f, void *opaque) } qemu_put_be32(f, env->cp15.c6_insn); qemu_put_be32(f, env->cp15.c6_data); - qemu_put_be32(f, env->cp15.c7_par); + qemu_put_be64(f, env->cp15.c7_par); qemu_put_be32(f, env->cp15.c9_insn); qemu_put_be32(f, env->cp15.c9_data); qemu_put_be32(f, env->cp15.c9_pmcr); @@ -145,11 +143,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->cp15.c1_coproc = qemu_get_be32(f); env->cp15.c1_xscaleauxcr = qemu_get_be32(f); env->cp15.c1_scr = qemu_get_be32(f); - env->cp15.c2_base0 = qemu_get_be32(f); - env->cp15.c2_base1 = qemu_get_be32(f); + env->cp15.c2_base0 = qemu_get_be64(f); + env->cp15.c2_base1 = qemu_get_be64(f); env->cp15.c2_control = qemu_get_be32(f); - env->cp15.c2_mask = qemu_get_be32(f); - env->cp15.c2_base_mask = qemu_get_be32(f); env->cp15.c2_data = qemu_get_be32(f); env->cp15.c2_insn = qemu_get_be32(f); env->cp15.c3 = qemu_get_be32(f); @@ -160,7 +156,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) } env->cp15.c6_insn = qemu_get_be32(f); env->cp15.c6_data = qemu_get_be32(f); - env->cp15.c7_par = qemu_get_be32(f); + env->cp15.c7_par = qemu_get_be64(f); env->cp15.c9_insn = qemu_get_be32(f); env->cp15.c9_data = qemu_get_be32(f); env->cp15.c9_pmcr = qemu_get_be32(f);