@@ -36,7 +36,7 @@ typedef struct CPULM32State CPULM32State;
#define NB_MMU_MODES 1
#define TARGET_PAGE_BITS 12
-static inline int cpu_mmu_index(CPUState *env)
+static inline int cpu_mmu_index(CPULM32State *env)
{
return 0;
}
@@ -185,18 +185,18 @@ typedef struct CPULM32State {
} CPULM32State;
-CPUState *cpu_lm32_init(const char *cpu_model);
+CPULM32State *cpu_lm32_init(const char *cpu_model);
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
-int cpu_lm32_exec(CPUState *s);
-void cpu_lm32_close(CPUState *s);
-void do_interrupt(CPUState *env);
+int cpu_lm32_exec(CPULM32State *s);
+void cpu_lm32_close(CPULM32State *s);
+void do_interrupt(CPULM32State *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
int cpu_lm32_signal_handler(int host_signum, void *pinfo,
void *puc);
void lm32_translate_init(void);
-void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
+void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
#define cpu_list cpu_lm32_list
#define cpu_init cpu_lm32_init
@@ -206,12 +206,12 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
#define CPU_SAVE_VERSION 1
-int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPULM32State *env, target_ulong newsp)
{
if (newsp) {
env->regs[R_SP] = newsp;
@@ -220,23 +220,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
}
#endif
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPULM32State *env, target_ulong newtls)
{
}
-static inline int cpu_interrupts_enabled(CPUState *env)
+static inline int cpu_interrupts_enabled(CPULM32State *env)
{
return env->ie & IE_IE;
}
#include "cpu-all.h"
-static inline target_ulong cpu_get_pc(CPUState *env)
+static inline target_ulong cpu_get_pc(CPULM32State *env)
{
return env->pc;
}
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
@@ -244,14 +244,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*flags = 0;
}
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPULM32State *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPULM32State *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
@@ -20,7 +20,7 @@
#include "cpu.h"
#include "host-utils.h"
-int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
int mmu_idx)
{
int prot;
@@ -37,12 +37,12 @@ int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
{
return addr & TARGET_PAGE_MASK;
}
-void do_interrupt(CPUState *env)
+void do_interrupt(CPULM32State *env)
{
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%x type=%x\n", env->pc, env->exception_index);
@@ -192,9 +192,9 @@ static uint32_t cfg_by_def(const LM32Def *def)
return cfg;
}
-CPUState *cpu_lm32_init(const char *cpu_model)
+CPULM32State *cpu_lm32_init(const char *cpu_model)
{
- CPUState *env;
+ CPULM32State *env;
const LM32Def *def;
static int tcg_initialized;
@@ -203,7 +203,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
return NULL;
}
- env = g_malloc0(sizeof(CPUState));
+ env = g_malloc0(sizeof(CPULM32State));
env->features = def->features;
env->num_bps = def->num_breakpoints;
@@ -226,7 +226,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
* area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
* 0x80000000-0xffffffff is not cached and used to access IO devices. */
-void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
+void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
{
if (value) {
env->flags |= LM32_FLAG_IGNORE_MSB;
@@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
}
}
-void cpu_state_reset(CPUState *env)
+void cpu_state_reset(CPULM32State *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -7,17 +7,17 @@ static const VMStateDescription vmstate_cpu = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
- VMSTATE_UINT32_ARRAY(regs, CPUState, 32),
- VMSTATE_UINT32(pc, CPUState),
- VMSTATE_UINT32(ie, CPUState),
- VMSTATE_UINT32(icc, CPUState),
- VMSTATE_UINT32(dcc, CPUState),
- VMSTATE_UINT32(cc, CPUState),
- VMSTATE_UINT32(eba, CPUState),
- VMSTATE_UINT32(dc, CPUState),
- VMSTATE_UINT32(deba, CPUState),
- VMSTATE_UINT32_ARRAY(bp, CPUState, 4),
- VMSTATE_UINT32_ARRAY(wp, CPUState, 4),
+ VMSTATE_UINT32_ARRAY(regs, CPULM32State, 32),
+ VMSTATE_UINT32(pc, CPULM32State),
+ VMSTATE_UINT32(ie, CPULM32State),
+ VMSTATE_UINT32(icc, CPULM32State),
+ VMSTATE_UINT32(dcc, CPULM32State),
+ VMSTATE_UINT32(cc, CPULM32State),
+ VMSTATE_UINT32(eba, CPULM32State),
+ VMSTATE_UINT32(dc, CPULM32State),
+ VMSTATE_UINT32(deba, CPULM32State),
+ VMSTATE_UINT32_ARRAY(bp, CPULM32State, 4),
+ VMSTATE_UINT32_ARRAY(wp, CPULM32State, 4),
VMSTATE_END_OF_LIST()
}
};
@@ -75,11 +75,11 @@ uint32_t helper_rcsr_jrx(void)
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPULM32State *saved_env;
unsigned long pc;
int ret;
@@ -64,7 +64,7 @@ enum {
/* This is the state at translation time. */
typedef struct DisasContext {
- CPUState *env;
+ CPULM32State *env;
target_ulong pc;
/* Decoder. */
@@ -987,7 +987,7 @@ static inline void decode(DisasContext *dc)
decinfo[dc->opcode](dc);
}
-static void check_breakpoint(CPUState *env, DisasContext *dc)
+static void check_breakpoint(CPULM32State *env, DisasContext *dc)
{
CPUBreakpoint *bp;
@@ -1003,7 +1003,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
}
/* generate intermediate code for basic block 'tb'. */
-static void gen_intermediate_code_internal(CPUState *env,
+static void gen_intermediate_code_internal(CPULM32State *env,
TranslationBlock *tb, int search_pc)
{
struct DisasContext ctx, *dc = &ctx;
@@ -1129,17 +1129,17 @@ static void gen_intermediate_code_internal(CPUState *env,
#endif
}
-void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPULM32State *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -1171,7 +1171,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n\n");
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
}
@@ -1184,48 +1184,48 @@ void lm32_translate_init(void)
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ offsetof(CPULM32State, regs[i]),
regnames[i]);
}
for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, bp[i]),
+ offsetof(CPULM32State, bp[i]),
regnames[32+i]);
}
for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, wp[i]),
+ offsetof(CPULM32State, wp[i]),
regnames[36+i]);
}
cpu_pc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, pc),
+ offsetof(CPULM32State, pc),
"pc");
cpu_ie = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, ie),
+ offsetof(CPULM32State, ie),
"ie");
cpu_icc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, icc),
+ offsetof(CPULM32State, icc),
"icc");
cpu_dcc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, dcc),
+ offsetof(CPULM32State, dcc),
"dcc");
cpu_cc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc),
+ offsetof(CPULM32State, cc),
"cc");
cpu_cfg = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cfg),
+ offsetof(CPULM32State, cfg),
"cfg");
cpu_eba = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, eba),
+ offsetof(CPULM32State, eba),
"eba");
cpu_dc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, dc),
+ offsetof(CPULM32State, dc),
"dc");
cpu_deba = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, deba),
+ offsetof(CPULM32State, deba),
"deba");
}