From patchwork Wed Mar 14 21:42:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 146777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6DC2BB6EEE for ; Thu, 15 Mar 2012 10:28:49 +1100 (EST) Received: from localhost ([::1]:35241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vzs-0006iy-HN for incoming@patchwork.ozlabs.org; Wed, 14 Mar 2012 17:44:40 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vyi-0004xr-34 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7vyI-0005Xo-QC for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:27 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34867 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vyI-0005XJ-GX; Wed, 14 Mar 2012 17:43:02 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 1F66B8FE2D; Wed, 14 Mar 2012 22:43:01 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 14 Mar 2012 22:42:14 +0100 Message-Id: <1331761376-20362-2-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331761376-20362-1-git-send-email-afaerber@suse.de> References: <1331761376-20362-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: "open list:PowerPC" , Alexander Graf , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH v5 01/43] PPC: 405: Use proper CPU reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexander Graf On ppc405ep there is a register that allows for software to reset the core, but not the whole system. Implement this reset using a reset interrupt. This gets rid of a bunch of #if 0'ed code. Reported-by: Andreas Färber Signed-off-by: Alexander Graf Signed-off-by: Andreas Färber --- cpu-exec.c | 2 -- hw/ppc.c | 13 ++----------- hw/ppc405_uc.c | 16 ++-------------- target-ppc/cpu.h | 3 +++ 4 files changed, 7 insertions(+), 27 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 2c2d24e..3d28053 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -339,11 +339,9 @@ int cpu_exec(CPUState *env) } } #elif defined(TARGET_PPC) -#if 0 if ((interrupt_request & CPU_INTERRUPT_RESET)) { cpu_reset(env); } -#endif if (interrupt_request & CPU_INTERRUPT_HARD) { ppc_hw_interrupt(env); if (env->pending_interrupts == 0) diff --git a/hw/ppc.c b/hw/ppc.c index 59882e2..a9516f1 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -131,13 +131,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) /* Level sensitive - active low */ if (level) { LOG_IRQ("%s: reset the CPU\n", __func__); - env->interrupt_request |= CPU_INTERRUPT_EXITTB; - /* XXX: TOFIX */ -#if 0 - cpu_reset(env); -#else - qemu_system_reset_request(); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); } break; case PPC6xx_INPUT_SRESET: @@ -214,10 +208,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level) case PPC970_INPUT_HRESET: /* Level sensitive - active low */ if (level) { -#if 0 // XXX: TOFIX - LOG_IRQ("%s: reset the CPU\n", __func__); - cpu_reset(env); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); } break; case PPC970_INPUT_SRESET: diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 98079fa..951b389 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -1769,13 +1769,7 @@ void ppc40x_core_reset (CPUState *env) target_ulong dbsr; printf("Reset PowerPC core\n"); - env->interrupt_request |= CPU_INTERRUPT_EXITTB; - /* XXX: TOFIX */ -#if 0 - cpu_reset(env); -#else - qemu_system_reset_request(); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); dbsr = env->spr[SPR_40x_DBSR]; dbsr &= ~0x00000300; dbsr |= 0x00000100; @@ -1787,13 +1781,7 @@ void ppc40x_chip_reset (CPUState *env) target_ulong dbsr; printf("Reset PowerPC chip\n"); - env->interrupt_request |= CPU_INTERRUPT_EXITTB; - /* XXX: TOFIX */ -#if 0 - cpu_reset(env); -#else - qemu_system_reset_request(); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); /* XXX: TODO reset all internal peripherals */ dbsr = env->spr[SPR_40x_DBSR]; dbsr &= ~0x00000300; diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index fbcf488..ac753f3 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2051,6 +2051,9 @@ enum { PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ }; +/* CPU should be reset next, restart from scratch afterwards */ +#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0 + /*****************************************************************************/ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,