From patchwork Wed Mar 14 21:42:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 146766 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 94FA4B6EEA for ; Thu, 15 Mar 2012 10:13:34 +1100 (EST) Received: from localhost ([::1]:35205 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vzj-0006iU-ML for incoming@patchwork.ozlabs.org; Wed, 14 Mar 2012 17:44:31 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vye-0004l5-9u for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7vyX-0005eM-Ro for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:23 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34923 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vyX-0005dh-F1 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:17 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 45E3590B1D; Wed, 14 Mar 2012 22:43:16 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 14 Mar 2012 22:42:35 +0100 Message-Id: <1331761376-20362-23-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331761376-20362-1-git-send-email-afaerber@suse.de> References: <1331761376-20362-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Subject: [Qemu-devel] [PATCH v5 22/43] target-sh4: Don't overuse CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Scripted conversion: sed -i "s/CPUState/CPUSH4State/g" target-sh4/*.[hc] sed -i "s/#define CPUSH4State/#define CPUState/" target-sh4/cpu.h Signed-off-by: Andreas Färber Acked-by: Anthony Liguori --- target-sh4/cpu.h | 10 +++++----- target-sh4/helper.c | 28 ++++++++++++++-------------- target-sh4/op_helper.c | 4 ++-- target-sh4/translate.c | 46 +++++++++++++++++++++++----------------------- 4 files changed, 44 insertions(+), 44 deletions(-) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 7d7fdde..b45e54f 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -240,13 +240,13 @@ void cpu_load_tlb(CPUSH4State * env); #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUState *env) +static inline int cpu_mmu_index (CPUSH4State *env) { return (env->sr & SR_MD) == 0 ? 1 : 0; } #if defined(CONFIG_USER_ONLY) -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp) { if (newsp) env->gregs[15] = newsp; @@ -348,7 +348,7 @@ static inline int cpu_ptel_pr (uint32_t ptel) #define TB_FLAG_PENDING_MOVCA (1 << 4) -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, +static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, target_ulong *cs_base, int *flags) { *pc = env->pc; @@ -361,14 +361,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ } -static inline bool cpu_has_work(CPUState *env) +static inline bool cpu_has_work(CPUSH4State *env) { return env->interrupt_request & CPU_INTERRUPT_HARD; } #include "exec-all.h" -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb) { env->pc = tb->pc; env->flags = tb->flags; diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 006d1a9..5c57380 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -31,12 +31,12 @@ #if defined(CONFIG_USER_ONLY) -void do_interrupt (CPUState *env) +void do_interrupt (CPUSH4State *env) { env->exception_index = -1; } -int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, +int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, int mmu_idx) { env->tea = address; @@ -78,7 +78,7 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) -void do_interrupt(CPUState * env) +void do_interrupt(CPUSH4State * env) { int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD; int do_exp, irq_vector = env->exception_index; @@ -202,7 +202,7 @@ void do_interrupt(CPUState * env) } } -static void update_itlb_use(CPUState * env, int itlbnb) +static void update_itlb_use(CPUSH4State * env, int itlbnb) { uint8_t or_mask = 0, and_mask = (uint8_t) - 1; @@ -227,7 +227,7 @@ static void update_itlb_use(CPUState * env, int itlbnb) env->mmucr |= (or_mask << 24); } -static int itlb_replacement(CPUState * env) +static int itlb_replacement(CPUSH4State * env) { if ((env->mmucr & 0xe0000000) == 0xe0000000) return 0; @@ -243,7 +243,7 @@ static int itlb_replacement(CPUState * env) /* Find the corresponding entry in the right TLB Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE */ -static int find_tlb_entry(CPUState * env, target_ulong address, +static int find_tlb_entry(CPUSH4State * env, target_ulong address, tlb_t * entries, uint8_t nbtlb, int use_asid) { int match = MMU_DTLB_MISS; @@ -269,7 +269,7 @@ static int find_tlb_entry(CPUState * env, target_ulong address, return match; } -static void increment_urc(CPUState * env) +static void increment_urc(CPUSH4State * env) { uint8_t urb, urc; @@ -285,7 +285,7 @@ static void increment_urc(CPUState * env) /* Copy and utlb entry into itlb Return entry */ -static int copy_utlb_entry_itlb(CPUState *env, int utlb) +static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) { int itlb; @@ -303,7 +303,7 @@ static int copy_utlb_entry_itlb(CPUState *env, int utlb) /* Find itlb entry Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE */ -static int find_itlb_entry(CPUState * env, target_ulong address, +static int find_itlb_entry(CPUSH4State * env, target_ulong address, int use_asid) { int e; @@ -321,7 +321,7 @@ static int find_itlb_entry(CPUState * env, target_ulong address, /* Find utlb entry Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ -static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) +static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid) { /* per utlb access */ increment_urc(env); @@ -337,7 +337,7 @@ static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION, MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE. */ -static int get_mmu_address(CPUState * env, target_ulong * physical, +static int get_mmu_address(CPUSH4State * env, target_ulong * physical, int *prot, target_ulong address, int rw, int access_type) { @@ -403,7 +403,7 @@ static int get_mmu_address(CPUState * env, target_ulong * physical, return n; } -static int get_physical_address(CPUState * env, target_ulong * physical, +static int get_physical_address(CPUSH4State * env, target_ulong * physical, int *prot, target_ulong address, int rw, int access_type) { @@ -442,7 +442,7 @@ static int get_physical_address(CPUState * env, target_ulong * physical, return get_mmu_address(env, physical, prot, address, rw, access_type); } -int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, +int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, int mmu_idx) { target_ulong physical; @@ -503,7 +503,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, return 0; } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +target_phys_addr_t cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr) { target_ulong physical; int prot; diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index b299576..30f762f 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -55,10 +55,10 @@ static void cpu_restore_state_from_retaddr(void *retaddr) #define SHIFT 3 #include "softmmu_template.h" -void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx, void *retaddr) { - CPUState *saved_env; + CPUSH4State *saved_env; int ret; saved_env = env; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c385de8..a337beb 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -103,47 +103,47 @@ static void sh4_translate_init(void) for (i = 0; i < 24; i++) cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, gregs[i]), + offsetof(CPUSH4State, gregs[i]), gregnames[i]); cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, pc), "PC"); + offsetof(CPUSH4State, pc), "PC"); cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, sr), "SR"); + offsetof(CPUSH4State, sr), "SR"); cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, ssr), "SSR"); + offsetof(CPUSH4State, ssr), "SSR"); cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, spc), "SPC"); + offsetof(CPUSH4State, spc), "SPC"); cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, gbr), "GBR"); + offsetof(CPUSH4State, gbr), "GBR"); cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, vbr), "VBR"); + offsetof(CPUSH4State, vbr), "VBR"); cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, sgr), "SGR"); + offsetof(CPUSH4State, sgr), "SGR"); cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, dbr), "DBR"); + offsetof(CPUSH4State, dbr), "DBR"); cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, mach), "MACH"); + offsetof(CPUSH4State, mach), "MACH"); cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, macl), "MACL"); + offsetof(CPUSH4State, macl), "MACL"); cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, pr), "PR"); + offsetof(CPUSH4State, pr), "PR"); cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, fpscr), "FPSCR"); + offsetof(CPUSH4State, fpscr), "FPSCR"); cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, fpul), "FPUL"); + offsetof(CPUSH4State, fpul), "FPUL"); cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, flags), "_flags_"); + offsetof(CPUSH4State, flags), "_flags_"); cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, delayed_pc), + offsetof(CPUSH4State, delayed_pc), "_delayed_pc_"); cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, ldst), "_ldst_"); + offsetof(CPUSH4State, ldst), "_ldst_"); for (i = 0; i < 32; i++) cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, fregs[i]), + offsetof(CPUSH4State, fregs[i]), fregnames[i]); /* register helpers */ @@ -153,7 +153,7 @@ static void sh4_translate_init(void) done_init = 1; } -void cpu_dump_state(CPUState * env, FILE * f, +void cpu_dump_state(CPUSH4State * env, FILE * f, int (*cpu_fprintf) (FILE * f, const char *fmt, ...), int flags) { @@ -1918,7 +1918,7 @@ static void decode_opc(DisasContext * ctx) } static inline void -gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, +gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, int search_pc) { DisasContext ctx; @@ -2044,17 +2044,17 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, #endif } -void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 0); } -void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) +void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 1); } -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) +void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos) { env->pc = gen_opc_pc[pc_pos]; env->flags = gen_opc_hflags[pc_pos];