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Wed, 14 Mar 2012 17:43:35 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34935 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7vyb-0005g4-4j for qemu-devel@nongnu.org; Wed, 14 Mar 2012 17:43:21 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 0129290B49 for ; Wed, 14 Mar 2012 22:43:20 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 14 Mar 2012 22:42:42 +0100 Message-Id: <1331761376-20362-30-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331761376-20362-1-git-send-email-afaerber@suse.de> References: <1331761376-20362-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH v5 29/43] alpha hw/: Don't use CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Scripted conversion: for file in hw/alpha_*.[hc]; do sed -i "s/CPUState/CPUAlphaState/g" $file done Signed-off-by: Andreas Färber Acked-by: Anthony Liguori --- hw/alpha_dp264.c | 2 +- hw/alpha_sys.h | 2 +- hw/alpha_typhoon.c | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c index ea0fd95..9eb939f 100644 --- a/hw/alpha_dp264.c +++ b/hw/alpha_dp264.c @@ -49,7 +49,7 @@ static void clipper_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *cpus[4]; + CPUAlphaState *cpus[4]; PCIBus *pci_bus; ISABus *isa_bus; qemu_irq rtc_irq; diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h index f9506c6..de40f8b 100644 --- a/hw/alpha_sys.h +++ b/hw/alpha_sys.h @@ -11,7 +11,7 @@ #include "irq.h" -PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUState *[4], +PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[4], pci_map_irq_fn); /* alpha_pci.c. */ diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index b539416..872e112 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -21,7 +21,7 @@ typedef struct TyphoonCchip { uint64_t drir; uint64_t dim[4]; uint32_t iic[4]; - CPUState *cpu[4]; + CPUAlphaState *cpu[4]; } TyphoonCchip; typedef struct TyphoonWindow { @@ -52,7 +52,7 @@ typedef struct TyphoonState { } TyphoonState; /* Called when one of DRIR or DIM changes. */ -static void cpu_irq_change(CPUState *env, uint64_t req) +static void cpu_irq_change(CPUAlphaState *env, uint64_t req) { /* If there are any non-masked interrupts, tell the cpu. */ if (env) { @@ -66,7 +66,7 @@ static void cpu_irq_change(CPUState *env, uint64_t req) static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size) { - CPUState *env = cpu_single_env; + CPUAlphaState *env = cpu_single_env; TyphoonState *s = opaque; uint64_t ret = 0; @@ -347,7 +347,7 @@ static void cchip_write(void *opaque, target_phys_addr_t addr, if ((newval ^ oldval) & 0xff0) { int i; for (i = 0; i < 4; ++i) { - CPUState *env = s->cchip.cpu[i]; + CPUAlphaState *env = s->cchip.cpu[i]; if (env) { /* IPI can be either cleared or set by the write. */ if (newval & (1 << (i + 8))) { @@ -655,7 +655,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) /* Deliver the interrupt to each CPU, considering each CPU's IIC. */ for (i = 0; i < 4; ++i) { - CPUState *env = s->cchip.cpu[i]; + CPUAlphaState *env = s->cchip.cpu[i]; if (env) { uint32_t iic = s->cchip.iic[i]; @@ -693,7 +693,7 @@ static void typhoon_alarm_timer(void *opaque) PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, qemu_irq *p_rtc_irq, - CPUState *cpus[4], pci_map_irq_fn sys_map_irq) + CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq) { const uint64_t MB = 1024 * 1024; const uint64_t GB = 1024 * MB; @@ -713,7 +713,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, /* Remember the CPUs so that we can deliver interrupts to them. */ for (i = 0; i < 4; i++) { - CPUState *env = cpus[i]; + CPUAlphaState *env = cpus[i]; s->cchip.cpu[i] = env; if (env) { env->alarm_timer = qemu_new_timer_ns(rtc_clock,