From patchwork Tue Mar 13 16:59:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Nelson X-Patchwork-Id: 146447 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 92118B6FD2 for ; Wed, 14 Mar 2012 04:00:00 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7005B28085; Tue, 13 Mar 2012 17:59:57 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jePBphA3B-Tz; Tue, 13 Mar 2012 17:59:57 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5305B2807D; Tue, 13 Mar 2012 17:59:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 36F0B2807D for ; Tue, 13 Mar 2012 17:59:50 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PFBZ+pw86MG7 for ; Tue, 13 Mar 2012 17:59:46 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.integraonline.com (relay2.integra.net [204.130.255.181]) by theia.denx.de (Postfix) with SMTP id 831452807B for ; Tue, 13 Mar 2012 17:59:44 +0100 (CET) Received: (qmail 1060 invoked from network); 13 Mar 2012 16:59:41 -0000 Received: from unknown (HELO ericsony.example.org) (70.96.116.236) by relay2.integra.net with SMTP; 13 Mar 2012 16:59:41 -0000 From: Eric Nelson To: u-boot@lists.denx.de Date: Tue, 13 Mar 2012 09:59:38 -0700 Message-Id: <1331657978-19270-1-git-send-email-eric.nelson@boundarydevices.com> X-Mailer: git-send-email 1.7.9 In-Reply-To: References: Cc: dirk.behme@de.bosch.com, wg@denx.de Subject: [U-Boot] [PATCH V2] i.MX6: mx6q_sabrelite: add SATA bindings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Eric Nelson --- This patch requires Stefano's driver for MX5/MX6. http://lists.denx.de/pipermail/u-boot/2012-February/118530.html V2 updated based on comments from the ML: - uses data structures imx_ccm_reg and iomuxc_base_regs for register offsets and constants from imx-regs.h and iomux-v3.h - moves setup_sata() from board_early_init_f() into board_init() arch/arm/include/asm/arch-mx6/imx-regs.h | 9 ++ arch/arm/include/asm/arch-mx6/iomux-v3.h | 101 +++++++++++++++++++++++++ board/freescale/mx6qsabrelite/mx6qsabrelite.c | 59 ++++++++++++++ include/configs/mx6qsabrelite.h | 13 +++ 4 files changed, 182 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3e5c4c2..c450afb 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -297,5 +297,14 @@ struct aipstz_regs { u32 opacr4; }; +struct iomuxc_base_regs { + u32 gpr[14]; /* 0x000 */ + u32 obsrv[5]; /* 0x038 */ + u32 swmux_ctl[197]; /* 0x04c */ + u32 swpad_ctl[250]; /* 0x360 */ + u32 swgrp[26]; /* 0x748 */ + u32 daisy[104]; /* 0x7b0..94c */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/iomux-v3.h b/arch/arm/include/asm/arch-mx6/iomux-v3.h index 4558f4f..a3e0169 100644 --- a/arch/arm/include/asm/arch-mx6/iomux-v3.h +++ b/arch/arm/include/asm/arch-mx6/iomux-v3.h @@ -100,4 +100,105 @@ typedef u64 iomux_v3_cfg_t; int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); +/* + * IOMUXC_GPR13 bit fields + */ +#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) +#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) +#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) +#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) +#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) +#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) +#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 +#define IOMUXC_GPR13_SATA_PHY_6_MASK (7< #include #include +#include #include #include #include @@ -267,6 +268,60 @@ int board_eth_init(bd_t *bis) return 0; } +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + u32 reg = 0; + s32 timeout = 100000; + struct imx_ccm_reg *const imx_ccm + = (struct imx_ccm_reg *) CCM_BASE_ADDR; + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + + /* Enable sata clock */ + reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ + reg |= MXC_CCM_CCGR5_CG2_MASK; + writel(reg, &imx_ccm->CCGR5); + + /* Enable PLLs */ + reg = readl(&imx_ccm->analog_pll_enet); + reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; + writel(reg, &imx_ccm->analog_pll_enet); + reg |= BM_ANADIG_PLL_SYS_ENABLE; + while (timeout--) { + if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) + break; + } + if (timeout <= 0) + return -1; + reg &= ~BM_ANADIG_PLL_SYS_BYPASS; + writel(reg, &imx_ccm->analog_pll_enet); + reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; + writel(reg, &imx_ccm->analog_pll_enet); + + /* Enable sata phy */ + reg = readl(&iomuxc_regs->gpr[13]) + & (IOMUXC_GPR13_SDMA_STOP_REQ + |IOMUXC_GPR13_CAN2_STOP_REQ + |IOMUXC_GPR13_CAN1_STOP_REQ + |IOMUXC_GPR13_ENET_STOP_REQ); + + reg |= IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<gpr[13]); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -283,6 +338,10 @@ int board_init(void) setup_spi(); #endif +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; } diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index c851559..a3c97c6 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -71,6 +71,19 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_SATA +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII