From patchwork Sat Mar 10 16:53:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 145873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DA8B2B6FA3 for ; Sun, 11 Mar 2012 04:05:23 +1100 (EST) Received: from localhost ([::1]:44004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PZT-0008Ga-9q for incoming@patchwork.ozlabs.org; Sat, 10 Mar 2012 11:55:07 -0500 Received: from eggs.gnu.org ([208.118.235.92]:41605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYb-0006Xm-0j for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6PYY-0001UV-Rp for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:12 -0500 Received: from cantor2.suse.de ([195.135.220.15]:42665 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6PYY-0001Tx-Di for qemu-devel@nongnu.org; Sat, 10 Mar 2012 11:54:10 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 3AFE0A22BB; Sat, 10 Mar 2012 17:54:09 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sat, 10 Mar 2012 17:53:51 +0100 Message-Id: <1331398436-20761-16-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331398436-20761-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331398436-20761-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR in ARMCPUClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Andreas Färber Cc: Peter Maydell --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 6 ++++++ target-arm/helper.c | 3 --- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index cd711fa..101cdb1 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -49,6 +49,7 @@ typedef struct ARMCPUClass { struct { uint32_t c0_cpuid; uint32_t c0_cachetype; + uint32_t c0_clid; uint32_t c0_c1[8]; uint32_t c0_c2[8]; uint32_t c1_sys; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 850aff1..1a06c52 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -47,6 +47,7 @@ static void arm_cpu_reset(CPUState *c) /* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */ env->cp15.c0_cachetype = klass->cp15.c0_cachetype; + env->cp15.c0_clid = klass->cp15.c0_clid; memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t)); env->vfp.xregs[ARM_VFP_MVFR0] = klass->vfp.mvfr[0]; @@ -177,6 +178,7 @@ typedef struct ARMCPUInfo { const char *name; uint32_t id; uint32_t cp15_c0_cachetype; + uint32_t cp15_c0_clid; uint32_t cp15_c0_c1[8]; uint32_t cp15_c0_c2[8]; uint32_t cp15_c1_sys; @@ -364,6 +366,7 @@ static const ARMCPUInfo arm_cpus[] = { .name = "cortex-a8", .id = 0x410fc080, .cp15_c0_cachetype = 0x82048004, + .cp15_c0_clid = (1 << 27) | (2 << 24) | 3, .cp15_c0_c1 = { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 @@ -384,6 +387,7 @@ static const ARMCPUInfo arm_cpus[] = { .name = "cortex-a9", .id = 0x410fc090, .cp15_c0_cachetype = 0x80038003, + .cp15_c0_clid = (1 << 27) | (1 << 24) | 3, .cp15_c0_c1 = { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 @@ -410,6 +414,7 @@ static const ARMCPUInfo arm_cpus[] = { .name = "cortex-a15", .id = 0x412fc0f1, .cp15_c0_cachetype = 0x8444c004, + .cp15_c0_clid = 0x0a200023, .cp15_c0_c1 = { 0x00001131, 0x00011011, 0x02010555, 0x00000000, 0x10201105, 0x20000000, 0x01240000, 0x02102211 @@ -542,6 +547,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data) k->cp15.c0_cpuid = info->id; k->cp15.c0_cachetype = info->cp15_c0_cachetype; + k->cp15.c0_clid = info->cp15_c0_clid; memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t)); k->cp15.c1_sys = info->cp15_c1_sys; diff --git a/target-arm/helper.c b/target-arm/helper.c index 1f5043c..1e3576c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -9,18 +9,15 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_CORTEXA8: - env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ break; case ARM_CPUID_CORTEXA9: - env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ break; case ARM_CPUID_CORTEXA15: - env->cp15.c0_clid = 0x0a200023; env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */