From patchwork Sat Mar 10 02:27:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 145836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 15745B6F13 for ; Sat, 10 Mar 2012 15:48:47 +1100 (EST) Received: from localhost ([::1]:46448 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C4n-0001ro-On for incoming@patchwork.ozlabs.org; Fri, 09 Mar 2012 21:30:33 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55305) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3r-0007zp-JH for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6C3m-0001RT-Rw for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:35 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39834 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3m-0001R2-Fx for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:30 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 62F028FC92 for ; Sat, 10 Mar 2012 03:29:29 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sat, 10 Mar 2012 03:27:47 +0100 Message-Id: <1331346496-10736-16-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331346496-10736-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH RFC v4 15/44] target-cris: Don't overuse CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Scripted conversion: sed -i "s/CPUState/CPUCRISState/g" target-cris/*.[hc] sed -i "s/#define CPUCRISState/#define CPUState/" target-cris/cpu.h Signed-off-by: Andreas Färber --- target-cris/cpu.h | 12 +++++----- target-cris/helper.c | 14 ++++++------ target-cris/mmu.c | 14 ++++++------ target-cris/mmu.h | 6 ++-- target-cris/op_helper.c | 6 ++-- target-cris/translate.c | 46 +++++++++++++++++++++--------------------- target-cris/translate_v10.c | 26 ++++++++++++------------ 7 files changed, 62 insertions(+), 62 deletions(-) diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 222a062..f38393a 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -225,17 +225,17 @@ enum { #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUState *env) +static inline int cpu_mmu_index (CPUCRISState *env) { return !!(env->pregs[PR_CCS] & U_FLAG); } -int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw, +int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault #if defined(CONFIG_USER_ONLY) -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp) { if (newsp) env->regs[14] = newsp; @@ -260,7 +260,7 @@ static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls) #include "cpu-all.h" -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, +static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { *pc = env->pc; @@ -273,14 +273,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, #define cpu_list cris_cpu_list void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf); -static inline bool cpu_has_work(CPUState *env) +static inline bool cpu_has_work(CPUCRISState *env) { return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } #include "exec-all.h" -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb) { env->pc = tb->pc; } diff --git a/target-cris/helper.c b/target-cris/helper.c index dd7f18e..8680f43 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -36,13 +36,13 @@ #if defined(CONFIG_USER_ONLY) -void do_interrupt (CPUState *env) +void do_interrupt (CPUCRISState *env) { env->exception_index = -1; env->pregs[PR_ERP] = env->pc; } -int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, +int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw, int mmu_idx) { env->exception_index = 0xaa; @@ -54,7 +54,7 @@ int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, #else /* !CONFIG_USER_ONLY */ -static void cris_shift_ccs(CPUState *env) +static void cris_shift_ccs(CPUCRISState *env) { uint32_t ccs; /* Apply the ccs shift. */ @@ -63,7 +63,7 @@ static void cris_shift_ccs(CPUState *env) env->pregs[PR_CCS] = ccs; } -int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, +int cpu_cris_handle_mmu_fault (CPUCRISState *env, target_ulong address, int rw, int mmu_idx) { struct cris_mmu_result res; @@ -106,7 +106,7 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, return r; } -static void do_interruptv10(CPUState *env) +static void do_interruptv10(CPUCRISState *env) { int ex_vec = -1; @@ -162,7 +162,7 @@ static void do_interruptv10(CPUState *env) env->pregs[PR_ERP]); } -void do_interrupt(CPUState *env) +void do_interrupt(CPUCRISState *env) { int ex_vec = -1; @@ -246,7 +246,7 @@ void do_interrupt(CPUState *env) env->pregs[PR_ERP]); } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +target_phys_addr_t cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr) { uint32_t phy = addr; struct cris_mmu_result res; diff --git a/target-cris/mmu.c b/target-cris/mmu.c index 5cd8f27..512e28b 100644 --- a/target-cris/mmu.c +++ b/target-cris/mmu.c @@ -31,7 +31,7 @@ #define D_LOG(...) do { } while (0) #endif -void cris_mmu_init(CPUState *env) +void cris_mmu_init(CPUCRISState *env) { env->mmu_rand_lfsr = 0xcccc; } @@ -49,7 +49,7 @@ static inline unsigned int compute_polynom(unsigned int sr) return f; } -static void cris_mmu_update_rand_lfsr(CPUState *env) +static void cris_mmu_update_rand_lfsr(CPUCRISState *env) { unsigned int f; @@ -70,7 +70,7 @@ static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg) return (1 << seg) & rw_mm_cfg; } -static uint32_t cris_mmu_translate_seg(CPUState *env, int seg) +static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg) { uint32_t base; int i; @@ -106,7 +106,7 @@ static inline void set_field(uint32_t *dst, unsigned int val, } #ifdef DEBUG -static void dump_tlb(CPUState *env, int mmu) +static void dump_tlb(CPUCRISState *env, int mmu) { int set; int idx; @@ -128,7 +128,7 @@ static void dump_tlb(CPUState *env, int mmu) /* rw 0 = read, 1 = write, 2 = exec. */ static int cris_mmu_translate_page(struct cris_mmu_result *res, - CPUState *env, uint32_t vaddr, + CPUCRISState *env, uint32_t vaddr, int rw, int usermode, int debug) { unsigned int vpage; @@ -288,7 +288,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, return !match; } -void cris_mmu_flush_pid(CPUState *env, uint32_t pid) +void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { target_ulong vaddr; unsigned int idx; @@ -323,7 +323,7 @@ void cris_mmu_flush_pid(CPUState *env, uint32_t pid) } int cris_mmu_translate(struct cris_mmu_result *res, - CPUState *env, uint32_t vaddr, + CPUCRISState *env, uint32_t vaddr, int rw, int mmu_idx, int debug) { int seg; diff --git a/target-cris/mmu.h b/target-cris/mmu.h index 459d809..8e249e8 100644 --- a/target-cris/mmu.h +++ b/target-cris/mmu.h @@ -10,8 +10,8 @@ struct cris_mmu_result int bf_vec; }; -void cris_mmu_init(CPUState *env); -void cris_mmu_flush_pid(CPUState *env, uint32_t pid); +void cris_mmu_init(CPUCRISState *env); +void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid); int cris_mmu_translate(struct cris_mmu_result *res, - CPUState *env, uint32_t vaddr, + CPUCRISState *env, uint32_t vaddr, int rw, int mmu_idx, int debug); diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 1eacc5f..c568e2b 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -56,11 +56,11 @@ NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx, void *retaddr) { TranslationBlock *tb; - CPUState *saved_env; + CPUCRISState *saved_env; unsigned long pc; int ret; @@ -201,7 +201,7 @@ void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg) env->regs[reg] = env->sregs[srs][sreg]; } -static void cris_ccs_rshift(CPUState *env) +static void cris_ccs_rshift(CPUCRISState *env) { uint32_t ccs; diff --git a/target-cris/translate.c b/target-cris/translate.c index f360c31..7224f46 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -74,7 +74,7 @@ static TCGv env_pc; /* This is the state at translation time. */ typedef struct DisasContext { - CPUState *env; + CPUCRISState *env; target_ulong pc, ppc; /* Decoder. */ @@ -160,9 +160,9 @@ static int preg_sizes[] = { }; #define t_gen_mov_TN_env(tn, member) \ - _t_gen_mov_TN_env((tn), offsetof(CPUState, member)) + _t_gen_mov_TN_env((tn), offsetof(CPUCRISState, member)) #define t_gen_mov_env_TN(member, tn) \ - _t_gen_mov_env_TN(offsetof(CPUState, member), (tn)) + _t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn)) static inline void t_gen_mov_TN_reg(TCGv tn, int r) { @@ -179,13 +179,13 @@ static inline void t_gen_mov_reg_TN(int r, TCGv tn) static inline void _t_gen_mov_TN_env(TCGv tn, int offset) { - if (offset > sizeof (CPUState)) + if (offset > sizeof (CPUCRISState)) fprintf(stderr, "wrong load from env from off=%d\n", offset); tcg_gen_ld_tl(tn, cpu_env, offset); } static inline void _t_gen_mov_env_TN(int offset, TCGv tn) { - if (offset > sizeof (CPUState)) + if (offset > sizeof (CPUCRISState)) fprintf(stderr, "wrong store to env at off=%d\n", offset); tcg_gen_st_tl(tn, cpu_env, offset); } @@ -3114,7 +3114,7 @@ static unsigned int crisv32_decoder(DisasContext *dc) return insn_len; } -static void check_breakpoint(CPUState *env, DisasContext *dc) +static void check_breakpoint(CPUCRISState *env, DisasContext *dc) { CPUBreakpoint *bp; @@ -3168,7 +3168,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc) /* generate intermediate code for basic block 'tb'. */ static void -gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, +gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb, int search_pc) { uint16_t *gen_opc_end; @@ -3419,17 +3419,17 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, #endif } -void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) +void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 0); } -void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) +void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 1); } -void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, +void cpu_dump_state (CPUCRISState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { int i; @@ -3532,41 +3532,41 @@ CPUCRISState *cpu_cris_init (const char *cpu_model) cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); cc_x = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_x), "cc_x"); + offsetof(CPUCRISState, cc_x), "cc_x"); cc_src = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_src), "cc_src"); + offsetof(CPUCRISState, cc_src), "cc_src"); cc_dest = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_dest), + offsetof(CPUCRISState, cc_dest), "cc_dest"); cc_result = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_result), + offsetof(CPUCRISState, cc_result), "cc_result"); cc_op = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_op), "cc_op"); + offsetof(CPUCRISState, cc_op), "cc_op"); cc_size = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_size), + offsetof(CPUCRISState, cc_size), "cc_size"); cc_mask = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_mask), + offsetof(CPUCRISState, cc_mask), "cc_mask"); env_pc = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, pc), + offsetof(CPUCRISState, pc), "pc"); env_btarget = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, btarget), + offsetof(CPUCRISState, btarget), "btarget"); env_btaken = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, btaken), + offsetof(CPUCRISState, btaken), "btaken"); for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, regs[i]), + offsetof(CPUCRISState, regs[i]), regnames[i]); } for (i = 0; i < 16; i++) { cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, pregs[i]), + offsetof(CPUCRISState, pregs[i]), pregnames[i]); } @@ -3596,7 +3596,7 @@ void cpu_state_reset(CPUCRISState *env) #endif } -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) +void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos) { env->pc = gen_opc_pc[pc_pos]; } diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index 95053b6..4ada3ed 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -1253,47 +1253,47 @@ static unsigned int crisv10_decoder(DisasContext *dc) return insn_len; } -static CPUCRISState *cpu_crisv10_init (CPUState *env) +static CPUCRISState *cpu_crisv10_init (CPUCRISState *env) { int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); cc_x = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_x), "cc_x"); + offsetof(CPUCRISState, cc_x), "cc_x"); cc_src = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_src), "cc_src"); + offsetof(CPUCRISState, cc_src), "cc_src"); cc_dest = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_dest), + offsetof(CPUCRISState, cc_dest), "cc_dest"); cc_result = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_result), + offsetof(CPUCRISState, cc_result), "cc_result"); cc_op = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_op), "cc_op"); + offsetof(CPUCRISState, cc_op), "cc_op"); cc_size = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_size), + offsetof(CPUCRISState, cc_size), "cc_size"); cc_mask = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, cc_mask), + offsetof(CPUCRISState, cc_mask), "cc_mask"); env_pc = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, pc), + offsetof(CPUCRISState, pc), "pc"); env_btarget = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, btarget), + offsetof(CPUCRISState, btarget), "btarget"); env_btaken = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, btaken), + offsetof(CPUCRISState, btaken), "btaken"); for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, regs[i]), + offsetof(CPUCRISState, regs[i]), regnames_v10[i]); } for (i = 0; i < 16; i++) { cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, pregs[i]), + offsetof(CPUCRISState, pregs[i]), pregnames_v10[i]); }