From patchwork Sat Mar 10 02:28:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 145806 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1A287B6F9F for ; Sat, 10 Mar 2012 14:50:44 +1100 (EST) Received: from localhost ([::1]:48712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C5w-00030y-Oh for incoming@patchwork.ozlabs.org; Fri, 09 Mar 2012 21:31:44 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C4I-0000SI-4H for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:30:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S6C3z-0001VT-SJ for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:30:01 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39857 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S6C3z-0001V6-6P for qemu-devel@nongnu.org; Fri, 09 Mar 2012 21:29:43 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 196E58FB75 for ; Sat, 10 Mar 2012 03:29:42 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sat, 10 Mar 2012 03:28:10 +0100 Message-Id: <1331346496-10736-39-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331346496-10736-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH RFC v4 38/44] ppc hw/: Don't use CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Scripted conversion: for file in hw/ppc*.[hc] hw/mpc8544_guts.c hw/spapr*.[hc] hw/virtex_ml507.c hw/xics.c; do sed -i "s/CPUState/CPUPPCState/g" $file done Signed-off-by: Andreas Färber --- hw/mpc8544_guts.c | 2 +- hw/ppc.c | 110 ++++++++++++++++++++++++------------------------ hw/ppc.h | 28 ++++++------ hw/ppc405.h | 8 ++-- hw/ppc405_uc.c | 34 +++++++------- hw/ppc440_bamboo.c | 6 +- hw/ppc4xx.h | 8 ++-- hw/ppc4xx_devs.c | 10 ++-- hw/ppc_booke.c | 20 ++++---- hw/ppc_newworld.c | 4 +- hw/ppc_oldworld.c | 4 +- hw/ppc_prep.c | 6 +- hw/ppce500_mpc8544ds.c | 12 +++--- hw/ppce500_spin.c | 8 ++-- hw/spapr.c | 10 ++-- hw/spapr.h | 4 +- hw/spapr_hcall.c | 42 +++++++++--------- hw/spapr_llan.c | 10 ++-- hw/spapr_rtas.c | 4 +- hw/spapr_vio.c | 12 +++--- hw/spapr_vty.c | 4 +- hw/virtex_ml507.c | 10 ++-- hw/xics.c | 10 ++-- 23 files changed, 183 insertions(+), 183 deletions(-) diff --git a/hw/mpc8544_guts.c b/hw/mpc8544_guts.c index aeb2de7..13b0ddd 100644 --- a/hw/mpc8544_guts.c +++ b/hw/mpc8544_guts.c @@ -62,7 +62,7 @@ static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr, unsigned size) { uint32_t value = 0; - CPUState *env = cpu_single_env; + CPUPPCState *env = cpu_single_env; addr &= MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { diff --git a/hw/ppc.c b/hw/ppc.c index a9516f1..98546de 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -47,10 +47,10 @@ # define LOG_TB(...) do { } while (0) #endif -static void cpu_ppc_tb_stop (CPUState *env); -static void cpu_ppc_tb_start (CPUState *env); +static void cpu_ppc_tb_stop (CPUPPCState *env); +static void cpu_ppc_tb_start (CPUPPCState *env); -void ppc_set_irq(CPUState *env, int n_IRQ, int level) +void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level) { unsigned int old_pending = env->pending_interrupts; @@ -77,7 +77,7 @@ void ppc_set_irq(CPUState *env, int n_IRQ, int level) /* PowerPC 6xx / 7xx internal IRQ controller */ static void ppc6xx_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -151,7 +151,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) } } -void ppc6xx_irq_init (CPUState *env) +void ppc6xx_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, PPC6xx_INPUT_NB); @@ -161,7 +161,7 @@ void ppc6xx_irq_init (CPUState *env) /* PowerPC 970 internal IRQ controller */ static void ppc970_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -233,7 +233,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level) } } -void ppc970_irq_init (CPUState *env) +void ppc970_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, PPC970_INPUT_NB); @@ -242,7 +242,7 @@ void ppc970_irq_init (CPUState *env) /* POWER7 internal IRQ controller */ static void power7_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, env, pin, level); @@ -266,7 +266,7 @@ static void power7_set_irq (void *opaque, int pin, int level) } } -void ppcPOWER7_irq_init (CPUState *env) +void ppcPOWER7_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env, POWER7_INPUT_NB); @@ -276,7 +276,7 @@ void ppcPOWER7_irq_init (CPUState *env) /* PowerPC 40x internal IRQ controller */ static void ppc40x_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -346,7 +346,7 @@ static void ppc40x_set_irq (void *opaque, int pin, int level) } } -void ppc40x_irq_init (CPUState *env) +void ppc40x_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, env, PPC40x_INPUT_NB); @@ -355,7 +355,7 @@ void ppc40x_irq_init (CPUState *env) /* PowerPC E500 internal IRQ controller */ static void ppce500_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -407,7 +407,7 @@ static void ppce500_set_irq (void *opaque, int pin, int level) } } -void ppce500_irq_init (CPUState *env) +void ppce500_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, env, PPCE500_INPUT_NB); @@ -421,7 +421,7 @@ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset; } -uint64_t cpu_ppc_load_tbl (CPUState *env) +uint64_t cpu_ppc_load_tbl (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -436,7 +436,7 @@ uint64_t cpu_ppc_load_tbl (CPUState *env) return tb; } -static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) +static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -447,7 +447,7 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) return tb >> 32; } -uint32_t cpu_ppc_load_tbu (CPUState *env) +uint32_t cpu_ppc_load_tbu (CPUPPCState *env) { if (kvm_enabled()) { return env->spr[SPR_TBU]; @@ -464,7 +464,7 @@ static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, __func__, value, *tb_offsetp); } -void cpu_ppc_store_tbl (CPUState *env, uint32_t value) +void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -475,7 +475,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value) &tb_env->tb_offset, tb | (uint64_t)value); } -static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) +static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -486,12 +486,12 @@ static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) &tb_env->tb_offset, ((uint64_t)value << 32) | tb); } -void cpu_ppc_store_tbu (CPUState *env, uint32_t value) +void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_tbu(env, value); } -uint64_t cpu_ppc_load_atbl (CPUState *env) +uint64_t cpu_ppc_load_atbl (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -502,7 +502,7 @@ uint64_t cpu_ppc_load_atbl (CPUState *env) return tb; } -uint32_t cpu_ppc_load_atbu (CPUState *env) +uint32_t cpu_ppc_load_atbu (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -513,7 +513,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env) return tb >> 32; } -void cpu_ppc_store_atbl (CPUState *env, uint32_t value) +void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -524,7 +524,7 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value) &tb_env->atb_offset, tb | (uint64_t)value); } -void cpu_ppc_store_atbu (CPUState *env, uint32_t value) +void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -535,7 +535,7 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value) &tb_env->atb_offset, ((uint64_t)value << 32) | tb); } -static void cpu_ppc_tb_stop (CPUState *env) +static void cpu_ppc_tb_stop (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb, atb, vmclk; @@ -557,7 +557,7 @@ static void cpu_ppc_tb_stop (CPUState *env) } } -static void cpu_ppc_tb_start (CPUState *env) +static void cpu_ppc_tb_start (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb, atb, vmclk; @@ -578,7 +578,7 @@ static void cpu_ppc_tb_start (CPUState *env) } } -static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) +static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) { ppc_tb_t *tb_env = env->tb_env; uint32_t decr; @@ -597,7 +597,7 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) return decr; } -uint32_t cpu_ppc_load_decr (CPUState *env) +uint32_t cpu_ppc_load_decr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; @@ -608,14 +608,14 @@ uint32_t cpu_ppc_load_decr (CPUState *env) return _cpu_ppc_load_decr(env, tb_env->decr_next); } -uint32_t cpu_ppc_load_hdecr (CPUState *env) +uint32_t cpu_ppc_load_hdecr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; return _cpu_ppc_load_decr(env, tb_env->hdecr_next); } -uint64_t cpu_ppc_load_purr (CPUState *env) +uint64_t cpu_ppc_load_purr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t diff; @@ -628,23 +628,23 @@ uint64_t cpu_ppc_load_purr (CPUState *env) /* When decrementer expires, * all we need to do is generate or queue a CPU exception */ -static inline void cpu_ppc_decr_excp(CPUState *env) +static inline void cpu_ppc_decr_excp(CPUPPCState *env) { /* Raise it */ LOG_TB("raise decrementer exception\n"); ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); } -static inline void cpu_ppc_hdecr_excp(CPUState *env) +static inline void cpu_ppc_hdecr_excp(CPUPPCState *env) { /* Raise it */ LOG_TB("raise decrementer exception\n"); ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); } -static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, +static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp, struct QEMUTimer *timer, - void (*raise_excp)(CPUState *), + void (*raise_excp)(CPUPPCState *), uint32_t decr, uint32_t value, int is_excp) { @@ -681,7 +681,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, } } -static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, +static inline void _cpu_ppc_store_decr(CPUPPCState *env, uint32_t decr, uint32_t value, int is_excp) { ppc_tb_t *tb_env = env->tb_env; @@ -690,7 +690,7 @@ static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, &cpu_ppc_decr_excp, decr, value, is_excp); } -void cpu_ppc_store_decr (CPUState *env, uint32_t value) +void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0); } @@ -700,7 +700,7 @@ static void cpu_ppc_decr_cb (void *opaque) _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); } -static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, +static inline void _cpu_ppc_store_hdecr(CPUPPCState *env, uint32_t hdecr, uint32_t value, int is_excp) { ppc_tb_t *tb_env = env->tb_env; @@ -711,7 +711,7 @@ static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, } } -void cpu_ppc_store_hdecr (CPUState *env, uint32_t value) +void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0); } @@ -721,7 +721,7 @@ static void cpu_ppc_hdecr_cb (void *opaque) _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); } -void cpu_ppc_store_purr (CPUState *env, uint64_t value) +void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value) { ppc_tb_t *tb_env = env->tb_env; @@ -731,7 +731,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value) static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) { - CPUState *env = opaque; + CPUPPCState *env = opaque; ppc_tb_t *tb_env = env->tb_env; tb_env->tb_freq = freq; @@ -746,7 +746,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) } /* Set up (once) timebase frequency (in Hz) */ -clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) +clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) { ppc_tb_t *tb_env; @@ -769,28 +769,28 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) /* Specific helpers for POWER & PowerPC 601 RTC */ #if 0 -static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env) +static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env) { return cpu_ppc_tb_init(env, 7812500); } #endif -void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value) +void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_tbu(env, value); } -uint32_t cpu_ppc601_load_rtcu (CPUState *env) +uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) { return _cpu_ppc_load_tbu(env); } -void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value) +void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) { cpu_ppc_store_tbl(env, value & 0x3FFFFF80); } -uint32_t cpu_ppc601_load_rtcl (CPUState *env) +uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) { return cpu_ppc_load_tbl(env) & 0x3FFFFF80; } @@ -814,7 +814,7 @@ struct ppc40x_timer_t { /* Fixed interval timer */ static void cpu_4xx_fit_cb (void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; uint64_t now, next; @@ -853,7 +853,7 @@ static void cpu_4xx_fit_cb (void *opaque) } /* Programmable interval timer */ -static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) +static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) { ppc40x_timer_t *ppc40x_timer; uint64_t now, next; @@ -882,7 +882,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) static void cpu_4xx_pit_cb (void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; @@ -904,7 +904,7 @@ static void cpu_4xx_pit_cb (void *opaque) /* Watchdog timer */ static void cpu_4xx_wdt_cb (void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; uint64_t now, next; @@ -969,7 +969,7 @@ static void cpu_4xx_wdt_cb (void *opaque) } } -void store_40x_pit (CPUState *env, target_ulong val) +void store_40x_pit (CPUPPCState *env, target_ulong val) { ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; @@ -981,14 +981,14 @@ void store_40x_pit (CPUState *env, target_ulong val) start_stop_pit(env, tb_env, 0); } -target_ulong load_40x_pit (CPUState *env) +target_ulong load_40x_pit (CPUPPCState *env) { return cpu_ppc_load_decr(env); } static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) { - CPUState *env = opaque; + CPUPPCState *env = opaque; ppc_tb_t *tb_env = env->tb_env; LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, @@ -998,7 +998,7 @@ static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) /* XXX: we should also update all timers */ } -clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq, +clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, unsigned int decr_excp) { ppc_tb_t *tb_env; @@ -1084,7 +1084,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) return -1; } -int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, +int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, dcr_read_cb dcr_read, dcr_write_cb dcr_write) { ppc_dcr_t *dcr_env; @@ -1107,7 +1107,7 @@ int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, return 0; } -int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), +int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), int (*write_error)(int dcrn)) { ppc_dcr_t *dcr_env; diff --git a/hw/ppc.h b/hw/ppc.h index 9f91170..2f3ea27 100644 --- a/hw/ppc.h +++ b/hw/ppc.h @@ -1,4 +1,4 @@ -void ppc_set_irq (CPUState *env, int n_IRQ, int level); +void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level); /* PowerPC hardware exceptions management helpers */ typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); @@ -43,32 +43,32 @@ struct ppc_tb_t { */ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset); -clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); +clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq); /* Embedded PowerPC DCR management */ typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn); typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val); -int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), +int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn), int (*dcr_write_error)(int dcrn)); -int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, +int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, dcr_read_cb drc_read, dcr_write_cb dcr_write); -clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq, +clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, unsigned int decr_excp); /* Embedded PowerPC reset */ -void ppc40x_core_reset (CPUState *env); -void ppc40x_chip_reset (CPUState *env); -void ppc40x_system_reset (CPUState *env); +void ppc40x_core_reset (CPUPPCState *env); +void ppc40x_chip_reset (CPUPPCState *env); +void ppc40x_system_reset (CPUPPCState *env); void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); extern CPUWriteMemoryFunc * const PPC_io_write[]; extern CPUReadMemoryFunc * const PPC_io_read[]; void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); -void ppc40x_irq_init (CPUState *env); -void ppce500_irq_init (CPUState *env); -void ppc6xx_irq_init (CPUState *env); -void ppc970_irq_init (CPUState *env); -void ppcPOWER7_irq_init (CPUState *env); +void ppc40x_irq_init (CPUPPCState *env); +void ppce500_irq_init (CPUPPCState *env); +void ppc6xx_irq_init (CPUPPCState *env); +void ppc970_irq_init (CPUPPCState *env); +void ppcPOWER7_irq_init (CPUPPCState *env); /* PPC machines for OpenBIOS */ enum { @@ -89,4 +89,4 @@ enum { #define PPC_SERIAL_MM_BAUDBASE 399193 /* ppc_booke.c */ -void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags); +void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags); diff --git a/hw/ppc405.h b/hw/ppc405.h index d8fdf09..1f5dc5f 100644 --- a/hw/ppc405.h +++ b/hw/ppc405.h @@ -56,23 +56,23 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, +ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags); -CPUState *ppc405cr_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[4], target_phys_addr_t ram_bases[4], target_phys_addr_t ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init); -CPUState *ppc405ep_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init); /* IBM STBxxx microcontrollers */ -CPUState *ppc_stb025_init (MemoryRegion ram_memories[2], +CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2], target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 951b389..6f8342e 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -41,7 +41,7 @@ #define DEBUG_CLOCKS //#define DEBUG_CLOCKS_LL -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, +ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) { ram_addr_t bdloc; @@ -169,7 +169,7 @@ static void ppc4xx_plb_reset (void *opaque) plb->besr = 0x00000000; } -static void ppc4xx_plb_init(CPUState *env) +static void ppc4xx_plb_init(CPUPPCState *env) { ppc4xx_plb_t *plb; @@ -245,7 +245,7 @@ static void ppc4xx_pob_reset (void *opaque) pob->besr[1] = 0x0000000; } -static void ppc4xx_pob_init(CPUState *env) +static void ppc4xx_pob_init(CPUPPCState *env) { ppc4xx_pob_t *pob; @@ -574,7 +574,7 @@ static void ebc_reset (void *opaque) ebc->cfg = 0x80400000; } -static void ppc405_ebc_init(CPUState *env) +static void ppc405_ebc_init(CPUPPCState *env) { ppc4xx_ebc_t *ebc; @@ -657,7 +657,7 @@ static void ppc405_dma_reset (void *opaque) dma->pol = 0x00000000; } -static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) +static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) { ppc405_dma_t *dma; @@ -960,7 +960,7 @@ static void ocm_reset (void *opaque) ocm->dsacntl = dsacntl; } -static void ppc405_ocm_init(CPUState *env) +static void ppc405_ocm_init(CPUPPCState *env) { ppc405_ocm_t *ocm; @@ -1713,7 +1713,7 @@ static void ppc40x_mal_reset (void *opaque) mal->txeobisr = 0x00000000; } -static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) +static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) { ppc40x_mal_t *mal; int i; @@ -1764,7 +1764,7 @@ static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) /*****************************************************************************/ /* SPR */ -void ppc40x_core_reset (CPUState *env) +void ppc40x_core_reset (CPUPPCState *env) { target_ulong dbsr; @@ -1776,7 +1776,7 @@ void ppc40x_core_reset (CPUState *env) env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_chip_reset (CPUState *env) +void ppc40x_chip_reset (CPUPPCState *env) { target_ulong dbsr; @@ -1789,13 +1789,13 @@ void ppc40x_chip_reset (CPUState *env) env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_system_reset (CPUState *env) +void ppc40x_system_reset (CPUPPCState *env) { printf("Reset PowerPC system\n"); qemu_system_reset_request(); } -void store_40x_dbcr0 (CPUState *env, uint32_t val) +void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) { switch ((val >> 28) & 0x3) { case 0x0: @@ -2066,7 +2066,7 @@ static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) cpc->psr |= D << 17; } -static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], +static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], uint32_t sysclk) { ppc405cr_cpc_t *cpc; @@ -2096,7 +2096,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], qemu_register_reset(ppc405cr_cpc_reset, cpc); } -CPUState *ppc405cr_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[4], target_phys_addr_t ram_bases[4], target_phys_addr_t ram_sizes[4], @@ -2105,7 +2105,7 @@ CPUState *ppc405cr_init(MemoryRegion *address_space_mem, { clk_setup_t clk_setup[PPC405CR_CLK_NB]; qemu_irq dma_irqs[4]; - CPUState *env; + CPUPPCState *env; qemu_irq *pic, *irqs; memset(clk_setup, 0, sizeof(clk_setup)); @@ -2408,7 +2408,7 @@ static void ppc405ep_cpc_reset (void *opaque) } /* XXX: sysclk should be between 25 and 100 MHz */ -static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], +static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], uint32_t sysclk) { ppc405ep_cpc_t *cpc; @@ -2445,7 +2445,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], #endif } -CPUState *ppc405ep_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], @@ -2454,7 +2454,7 @@ CPUState *ppc405ep_init(MemoryRegion *address_space_mem, { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; - CPUState *env; + CPUPPCState *env; qemu_irq *pic, *irqs; memset(clk_setup, 0, sizeof(clk_setup)); diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c index 835e36d..220c81d 100644 --- a/hw/ppc440_bamboo.c +++ b/hw/ppc440_bamboo.c @@ -121,7 +121,7 @@ out: } /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa) { @@ -145,7 +145,7 @@ static void mmubooke_create_initial_mapping(CPUState *env, static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; cpu_state_reset(env); env->gpr[1] = (16<<20) - 8; @@ -172,7 +172,7 @@ static void bamboo_init(ram_addr_t ram_size, qemu_irq *pic; qemu_irq *irqs; PCIBus *pcibus; - CPUState *env; + CPUPPCState *env; uint64_t elf_entry; uint64_t elf_lowaddr; target_phys_addr_t loadaddr = 0; diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h index f969e44..b511020 100644 --- a/hw/ppc4xx.h +++ b/hw/ppc4xx.h @@ -28,7 +28,7 @@ #include "pci.h" /* PowerPC 4xx core initialization */ -CPUState *ppc4xx_init (const char *cpu_model, +CPUPPCState *ppc4xx_init (const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk); @@ -38,7 +38,7 @@ enum { PPCUIC_OUTPUT_CINT = 1, PPCUIC_OUTPUT_NB, }; -qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, +qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, @@ -47,13 +47,13 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, target_phys_addr_t ram_sizes[], const unsigned int sdram_bank_sizes[]); -void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, +void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion ram_memories[], target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, int do_init); -PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], +PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4], target_phys_addr_t config_space, target_phys_addr_t int_ack, target_phys_addr_t special_cycle, diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 2311162..00e36f4 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -40,18 +40,18 @@ static void ppc4xx_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; cpu_state_reset(env); } /*****************************************************************************/ /* Generic PowerPC 4xx processor instantiation */ -CPUState *ppc4xx_init (const char *cpu_model, +CPUPPCState *ppc4xx_init (const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk) { - CPUState *env; + CPUPPCState *env; /* init CPUs */ env = cpu_init(cpu_model); @@ -295,7 +295,7 @@ static void ppcuic_reset (void *opaque) } } -qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, +qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr) { ppcuic_t *uic; @@ -641,7 +641,7 @@ static void sdram_reset (void *opaque) sdram->cfg = 0x00800000; } -void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, +void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion *ram_memories, target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, diff --git a/hw/ppc_booke.c b/hw/ppc_booke.c index 8871945..d51e7fa 100644 --- a/hw/ppc_booke.c +++ b/hw/ppc_booke.c @@ -71,7 +71,7 @@ struct booke_timer_t { uint32_t flags; }; -static void booke_update_irq(CPUState *env) +static void booke_update_irq(CPUPPCState *env) { ppc_set_irq(env, PPC_INTERRUPT_DECR, (env->spr[SPR_BOOKE_TSR] & TSR_DIS @@ -88,7 +88,7 @@ static void booke_update_irq(CPUState *env) /* Return the location of the bit of time base at which the FIT will raise an interrupt */ -static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env) +static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) { uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; @@ -106,7 +106,7 @@ static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env) /* Return the location of the bit of time base at which the WDT will raise an interrupt */ -static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env) +static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) { uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; @@ -122,7 +122,7 @@ static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env) return wp; } -static void booke_update_fixed_timer(CPUState *env, +static void booke_update_fixed_timer(CPUPPCState *env, uint8_t target_bit, uint64_t *next, struct QEMUTimer *timer) @@ -153,7 +153,7 @@ static void booke_update_fixed_timer(CPUState *env, static void booke_decr_cb(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; env->spr[SPR_BOOKE_TSR] |= TSR_DIS; booke_update_irq(env); @@ -166,7 +166,7 @@ static void booke_decr_cb(void *opaque) static void booke_fit_cb(void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; booke_timer_t *booke_timer; @@ -185,7 +185,7 @@ static void booke_fit_cb(void *opaque) static void booke_wdt_cb(void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; booke_timer_t *booke_timer; @@ -203,13 +203,13 @@ static void booke_wdt_cb(void *opaque) booke_timer->wdt_timer); } -void store_booke_tsr(CPUState *env, target_ulong val) +void store_booke_tsr(CPUPPCState *env, target_ulong val) { env->spr[SPR_BOOKE_TSR] &= ~val; booke_update_irq(env); } -void store_booke_tcr(CPUState *env, target_ulong val) +void store_booke_tcr(CPUPPCState *env, target_ulong val) { ppc_tb_t *tb_env = env->tb_env; booke_timer_t *booke_timer = tb_env->opaque; @@ -231,7 +231,7 @@ void store_booke_tcr(CPUState *env, target_ulong val) } -void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags) +void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags) { ppc_tb_t *tb_env; booke_timer_t *booke_timer; diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index fd8e21d..c60cfa0 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -124,7 +124,7 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) static void ppc_core99_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; cpu_state_reset(env); } @@ -137,7 +137,7 @@ static void ppc_core99_init (ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env = NULL; + CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; MemoryRegion *unin_memory = g_new(MemoryRegion, 1); diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index 085b825..36aaf97 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -68,7 +68,7 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) static void ppc_heathrow_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; cpu_state_reset(env); } @@ -81,7 +81,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, const char *cpu_model) { MemoryRegion *sysmem = get_system_memory(); - CPUState *env = NULL; + CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **heathrow_irqs; int linux_boot, i; diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index c5f2542..7a92f49 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -464,7 +464,7 @@ static const MemoryRegionOps PPC_prep_io_ops = { static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUPPCState *env = cpu_single_env; if (env && level) { cpu_exit(env); @@ -473,7 +473,7 @@ static void cpu_request_exit(void *opaque, int irq, int level) static void ppc_prep_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; cpu_state_reset(env); } @@ -487,7 +487,7 @@ static void ppc_prep_init (ram_addr_t ram_size, const char *cpu_model) { MemoryRegion *sysmem = get_system_memory(); - CPUState *env = NULL; + CPUPPCState *env = NULL; char *filename; nvram_t nvram; M48t59State *m48t59; diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index 752aed9..5ee8cb3 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -58,7 +58,7 @@ struct boot_info uint32_t entry; }; -static int mpc8544_load_device_tree(CPUState *env, +static int mpc8544_load_device_tree(CPUPPCState *env, target_phys_addr_t addr, uint32_t ramsize, target_phys_addr_t initrd_base, @@ -178,7 +178,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) return ffs(size >> 10) - 1; } -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa) { @@ -196,7 +196,7 @@ static void mmubooke_create_initial_mapping(CPUState *env, static void mpc8544ds_cpu_reset_sec(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; cpu_state_reset(env); @@ -208,7 +208,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque) static void mpc8544ds_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; struct boot_info *bi = env->load_info; cpu_state_reset(env); @@ -231,7 +231,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); PCIBus *pci_bus; - CPUState *env = NULL; + CPUPPCState *env = NULL; uint64_t elf_entry; uint64_t elf_lowaddr; target_phys_addr_t entry=0; @@ -244,7 +244,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; qemu_irq **irqs, *mpic; DeviceState *dev; - CPUState *firstenv = NULL; + CPUPPCState *firstenv = NULL; /* Setup CPUs */ if (cpu_model == NULL) { diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c index 6b8a189..268f5fd 100644 --- a/hw/ppce500_spin.c +++ b/hw/ppce500_spin.c @@ -49,7 +49,7 @@ typedef struct spin_state { } SpinState; typedef struct spin_kick { - CPUState *env; + CPUPPCState *env; SpinInfo *spin; } SpinKick; @@ -73,7 +73,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) return (ffs(size >> 10) - 1) >> 1; } -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa, target_phys_addr_t len) @@ -91,7 +91,7 @@ static void mmubooke_create_initial_mapping(CPUState *env, static void spin_kick(void *data) { SpinKick *kick = data; - CPUState *env = kick->env; + CPUPPCState *env = kick->env; SpinInfo *curspin = kick->spin; target_phys_addr_t map_size = 64 * 1024 * 1024; target_phys_addr_t map_start; @@ -121,7 +121,7 @@ static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value, { SpinState *s = opaque; int env_idx = addr / sizeof(SpinInfo); - CPUState *env; + CPUPPCState *env; SpinInfo *curspin = &s->spin[env_idx]; uint8_t *curspin_p = (uint8_t*)curspin; diff --git a/hw/spapr.c b/hw/spapr.c index 3f9d87c..3719e0e 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -110,7 +110,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num) static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr) { int ret = 0, offset; - CPUState *env; + CPUPPCState *env; char cpu_model[32]; int smt = kvmppc_smt_threads(); @@ -155,7 +155,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model, long hash_shift) { void *fdt; - CPUState *env; + CPUPPCState *env; uint64_t mem_reg_property[2]; uint32_t start_prop = cpu_to_be32(initrd_base); uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); @@ -476,7 +476,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; } -static void emulate_spapr_hypercall(CPUState *env) +static void emulate_spapr_hypercall(CPUPPCState *env) { env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); } @@ -504,7 +504,7 @@ static void spapr_reset(void *opaque) static void spapr_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; cpu_state_reset(env); } @@ -517,7 +517,7 @@ static void ppc_spapr_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUPPCState *env; int i; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); diff --git a/hw/spapr.h b/hw/spapr.h index e946a34..a41641f 100644 --- a/hw/spapr.h +++ b/hw/spapr.h @@ -278,12 +278,12 @@ extern sPAPREnvironment *spapr; do { } while (0) #endif -typedef target_ulong (*spapr_hcall_fn)(CPUState *env, sPAPREnvironment *spapr, +typedef target_ulong (*spapr_hcall_fn)(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args); void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); -target_ulong spapr_hypercall(CPUState *env, target_ulong opcode, +target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode, target_ulong *args); qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num); diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c index 6ac7384..634763e 100644 --- a/hw/spapr_hcall.c +++ b/hw/spapr_hcall.c @@ -92,7 +92,7 @@ static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, return rb; } -static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_enter(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; @@ -181,7 +181,7 @@ enum { REMOVE_HW = 3, }; -static target_ulong remove_hpte(CPUState *env, target_ulong ptex, +static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex, target_ulong avpn, target_ulong flags, target_ulong *vp, target_ulong *rp) @@ -219,7 +219,7 @@ static target_ulong remove_hpte(CPUState *env, target_ulong ptex, return REMOVE_SUCCESS; } -static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_remove(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; @@ -265,7 +265,7 @@ static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr, #define H_BULK_REMOVE_MAX_BATCH 4 -static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_bulk_remove(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { int i; @@ -311,7 +311,7 @@ static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_protect(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; @@ -356,7 +356,7 @@ static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_set_dabr(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* FIXME: actually implement this */ @@ -375,7 +375,7 @@ static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr, #define VPA_SHARED_PROC_OFFSET 0x9 #define VPA_SHARED_PROC_VAL 0x2 -static target_ulong register_vpa(CPUState *env, target_ulong vpa) +static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) { uint16_t size; uint8_t tmp; @@ -410,7 +410,7 @@ static target_ulong register_vpa(CPUState *env, target_ulong vpa) return H_SUCCESS; } -static target_ulong deregister_vpa(CPUState *env, target_ulong vpa) +static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) { if (env->slb_shadow) { return H_RESOURCE; @@ -424,7 +424,7 @@ static target_ulong deregister_vpa(CPUState *env, target_ulong vpa) return H_SUCCESS; } -static target_ulong register_slb_shadow(CPUState *env, target_ulong addr) +static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) { uint32_t size; @@ -451,13 +451,13 @@ static target_ulong register_slb_shadow(CPUState *env, target_ulong addr) return H_SUCCESS; } -static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr) +static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) { env->slb_shadow = 0; return H_SUCCESS; } -static target_ulong register_dtl(CPUState *env, target_ulong addr) +static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) { uint32_t size; @@ -482,7 +482,7 @@ static target_ulong register_dtl(CPUState *env, target_ulong addr) return H_SUCCESS; } -static target_ulong deregister_dtl(CPUState *emv, target_ulong addr) +static target_ulong deregister_dtl(CPUPPCState *emv, target_ulong addr) { env->dispatch_trace_log = 0; env->dtl_size = 0; @@ -490,14 +490,14 @@ static target_ulong deregister_dtl(CPUState *emv, target_ulong addr) return H_SUCCESS; } -static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_register_vpa(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; target_ulong procno = args[1]; target_ulong vpa = args[2]; target_ulong ret = H_PARAMETER; - CPUState *tenv; + CPUPPCState *tenv; for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) { if (tenv->cpu_index == procno) { @@ -538,7 +538,7 @@ static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr, return ret; } -static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_cede(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { env->msr |= (1ULL << MSR_EE); @@ -549,7 +549,7 @@ static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_rtas(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong rtas_r3 = args[0]; @@ -561,7 +561,7 @@ static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr, nret, rtas_r3 + 12 + 4*nargs); } -static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_load(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong size = args[0]; @@ -584,7 +584,7 @@ static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr, return H_PARAMETER; } -static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_store(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong size = args[0]; @@ -608,14 +608,14 @@ static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr, return H_PARAMETER; } -static target_ulong h_logical_icbi(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_icbi(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* Nothing to do on emulation, KVM will trap this in the kernel */ return H_SUCCESS; } -static target_ulong h_logical_dcbf(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_dcbf(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* Nothing to do on emulation, KVM will trap this in the kernel */ @@ -644,7 +644,7 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) *slot = fn; } -target_ulong spapr_hypercall(CPUState *env, target_ulong opcode, +target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode, target_ulong *args) { if (msr_pr) { diff --git a/hw/spapr_llan.c b/hw/spapr_llan.c index 77d4047..cfc7778 100644 --- a/hw/spapr_llan.c +++ b/hw/spapr_llan.c @@ -254,7 +254,7 @@ static int check_bd(VIOsPAPRVLANDevice *dev, vlan_bd_t bd, return 0; } -static target_ulong h_register_logical_lan(CPUState *env, +static target_ulong h_register_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) @@ -320,7 +320,7 @@ static target_ulong h_register_logical_lan(CPUState *env, } -static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_free_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -343,7 +343,7 @@ static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_add_logical_lan_buffer(CPUState *env, +static target_ulong h_add_logical_lan_buffer(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) @@ -392,7 +392,7 @@ static target_ulong h_add_logical_lan_buffer(CPUState *env, return H_SUCCESS; } -static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_send_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -461,7 +461,7 @@ static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_multicast_ctrl(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_multicast_ctrl(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c index c0723b3..0946585 100644 --- a/hw/spapr_rtas.c +++ b/hw/spapr_rtas.c @@ -118,7 +118,7 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr, uint32_t nret, target_ulong rets) { target_ulong id; - CPUState *env; + CPUPPCState *env; if (nargs != 1 || nret != 2) { rtas_st(rets, 0, -3); @@ -151,7 +151,7 @@ static void rtas_start_cpu(sPAPREnvironment *spapr, uint32_t nret, target_ulong rets) { target_ulong id, start, r3; - CPUState *env; + CPUPPCState *env; if (nargs != 3 || nret != 1) { rtas_st(rets, 0, -3); diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c index ea317ef..2fb3cee 100644 --- a/hw/spapr_vio.c +++ b/hw/spapr_vio.c @@ -194,7 +194,7 @@ static void rtce_init(VIOsPAPRDevice *dev) } } -static target_ulong h_put_tce(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_put_tce(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong liobn = args[0]; @@ -405,7 +405,7 @@ uint64_t ldq_tce(VIOsPAPRDevice *dev, uint64_t taddr) /* * CRQ handling */ -static target_ulong h_reg_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_reg_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -453,7 +453,7 @@ static target_ulong h_reg_crq(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_free_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_free_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -474,7 +474,7 @@ static target_ulong h_free_crq(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_send_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_send_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -498,7 +498,7 @@ static target_ulong h_send_crq(CPUState *env, sPAPREnvironment *spapr, return H_HARDWARE; } -static target_ulong h_enable_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_enable_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -680,7 +680,7 @@ static int spapr_vio_busdev_init(DeviceState *qdev) return pc->init(dev); } -static target_ulong h_vio_signal(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_vio_signal(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { diff --git a/hw/spapr_vty.c b/hw/spapr_vty.c index 3efe242..60e22b1 100644 --- a/hw/spapr_vty.c +++ b/hw/spapr_vty.c @@ -72,7 +72,7 @@ static int spapr_vty_init(VIOsPAPRDevice *sdev) /* Forward declaration */ static VIOsPAPRDevice *vty_lookup(sPAPREnvironment *spapr, target_ulong reg); -static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_put_term_char(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -99,7 +99,7 @@ static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_get_term_char(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_get_term_char(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c index e672490..4a133b5 100644 --- a/hw/virtex_ml507.c +++ b/hw/virtex_ml507.c @@ -56,7 +56,7 @@ static struct boot_info } boot_info; /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa) { @@ -78,12 +78,12 @@ static void mmubooke_create_initial_mapping(CPUState *env, tlb->PID = 0; } -static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size, +static CPUPPCState *ppc440_init_xilinx(ram_addr_t *ram_size, int do_init, const char *cpu_model, uint32_t sysclk) { - CPUState *env; + CPUPPCState *env; qemu_irq *irqs; env = cpu_init(cpu_model); @@ -106,7 +106,7 @@ static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size, static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; struct boot_info *bi = env->load_info; cpu_state_reset(env); @@ -188,7 +188,7 @@ static void virtex_init(ram_addr_t ram_size, { MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev; - CPUState *env; + CPUPPCState *env; target_phys_addr_t ram_base = 0; DriveInfo *dinfo; MemoryRegion *phys_ram = g_new(MemoryRegion, 1); diff --git a/hw/xics.c b/hw/xics.c index 1c5eaa4..f7963f3 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -268,7 +268,7 @@ qemu_irq xics_find_qirq(struct icp_state *icp, int irq) return icp->ics->qirqs[irq - icp->ics->offset]; } -static target_ulong h_cppr(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_cppr(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong cppr = args[0]; @@ -277,7 +277,7 @@ static target_ulong h_cppr(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_ipi(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong server = args[0]; @@ -292,7 +292,7 @@ static target_ulong h_ipi(CPUState *env, sPAPREnvironment *spapr, } -static target_ulong h_xirr(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_xirr(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index); @@ -301,7 +301,7 @@ static target_ulong h_xirr(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_eoi(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_eoi(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong xirr = args[0]; @@ -424,7 +424,7 @@ static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token, struct icp_state *xics_system_init(int nr_irqs) { - CPUState *env; + CPUPPCState *env; int max_server_num; int i; struct icp_state *icp;