Patchwork [11/18] nand/fsmc: Flip the bit only if the error index is < 4096

login
register
mail settings
Submitter Vipin Kumar
Date March 7, 2012, 11:30 a.m.
Message ID <8604c83bfbd5051c6e1ed2d10e726136419b3950.1331119143.git.vipin.kumar@st.com>
Download mbox | patch
Permalink /patch/145196/
State New
Headers show

Comments

Vipin Kumar - March 7, 2012, 11:30 a.m.
ECC can correct upto 8 bits in 512 bytes data + 13 bytes ecc. This means that
the algorithm can correct a max of 8 bits in 4200 bits ie the error indices can
be from 0 to 4199. Of these 0 to 4095 are for data and 4096 to 4199 for ecc.

The driver flips the bit only if the index is <= 4096. This is a bug since the
data bits are only from 0 to 4095.

This patch modifies the check as < 4096

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 drivers/mtd/nand/fsmc_nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Patch

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 5bc6410..9e9d90b 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -822,7 +822,7 @@  static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 		change_bit(0, (unsigned long *)&err_idx[i]);
 		change_bit(1, (unsigned long *)&err_idx[i]);
 
-		if (err_idx[i] <= chip->ecc.size * 8) {
+		if (err_idx[i] < chip->ecc.size * 8) {
 			change_bit(err_idx[i], (unsigned long *)dat);
 			i++;
 		}