[2/3] add SandyBridge CPU model
diff mbox

Message ID 1331057492-25105-3-git-send-email-ehabkost@redhat.com
State New
Headers show

Commit Message

Eduardo Habkost March 6, 2012, 6:11 p.m. UTC
This patches add the definition of a SandyBridge CPU model.

Summary of differences:

Flags present on actual hardware, but not on the added model definition:

- pbe, tm, ht, ss, acpi, vme, xTPR, tm2, eist, smx: host-specific
  features, not exposed to guest.
- ds, ds-cpl, dtes64, pdcm: emulation not supported by KVM (although it
  may be added in the future if implementing PMU virtualization)
- pcid, vmx, monitor: not emulated by Qemu/KVM right now.
- osxsave: set by the guest OS, not by Qemu.

Flags added, that were not present on Westmere model:

- xsave: already supported by Qemu
- avx, pclmulqdq: all new state the new instructions could use is
  handled by xsave state loading/saving code.
- tsc-deadline, x2apic, rdtscp: already supported by Qemu/KVM.

Below there's a comparison of the features on the current Westmere CPU
model, and the SandyBridge CPU model.

- The "full" line contains the flags found on actual hardware.
- The "missing" line shows the flags that are present on actual
  hardware, but not on the added SandyBridge model.
- The "new" line shows the flags that were not on the Westmere model,
  but are on SandyBridge.

feature_edx:
  Westmere:                 sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de     fpu
  full:        pbe tm ht ss sse2 sse fxsr mmx ds acpi clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pge msr tsc pse de vme fpu
  SandyBridge:              sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de     fpu
  missing:     pbe tm ht ss                   ds acpi                                                                         vme

feature_ecx:
  Westmere:                      aes              popcnt        sse4.2 sse4.1                cx16 ssse3                                                  sse3
  full:        avx osxsave xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 pcid pdcm xTPR cx16 ssse3 tm2 eist smx vmx ds-cpl monitor dtes64 pclmulqdq sse3
  SandyBridge: avx         xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1                cx16 ssse3                                        pclmulqdq sse3
  missing:         osxsave                                                    pcid pdcm xTPR            tm2 eist smx vmx ds-cpl monitor dtes64
  new:         avx         xsave     tsc-deadline        x2apic                                                                                pclmulqdq

extfeature_edx:
  Westmere:    i64        nx syscall
  full:        i64 rdtscp nx syscall
  SandyBridge: i64 rdtscp nx syscall
  new:             rdtscp

extfeature_ecx:
  Westmere:    lahf_lm
  full:        lahf_lm
  SandyBridge: lahf_lm

Cc: "Dugger, Donald D" <donald.d.dugger@intel.com>
Cc: "Zhang, Xiantao" <xiantao.zhang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

Comments

Zhang, Xiantao March 8, 2012, 8:12 a.m. UTC | #1
Seems fine! 
Acked-by: Xiantao Zhang <xiantao.zhang@intel.com>
Xiantao

> -----Original Message-----
> From: Eduardo Habkost [mailto:ehabkost@redhat.com]
> Sent: Wednesday, March 07, 2012 2:12 AM
> To: qemu-devel@nongnu.org
> Cc: Dugger, Donald D; Zhang, Xiantao
> Subject: [PATCH 2/3] add SandyBridge CPU model
> 
> This patches add the definition of a SandyBridge CPU model.
> 
> Summary of differences:
> 
> Flags present on actual hardware, but not on the added model definition:
> 
> - pbe, tm, ht, ss, acpi, vme, xTPR, tm2, eist, smx: host-specific
>   features, not exposed to guest.
> - ds, ds-cpl, dtes64, pdcm: emulation not supported by KVM (although it
>   may be added in the future if implementing PMU virtualization)
> - pcid, vmx, monitor: not emulated by Qemu/KVM right now.
> - osxsave: set by the guest OS, not by Qemu.
> 
> Flags added, that were not present on Westmere model:
> 
> - xsave: already supported by Qemu
> - avx, pclmulqdq: all new state the new instructions could use is
>   handled by xsave state loading/saving code.
> - tsc-deadline, x2apic, rdtscp: already supported by Qemu/KVM.
> 
> Below there's a comparison of the features on the current Westmere CPU
> model, and the SandyBridge CPU model.
> 
> - The "full" line contains the flags found on actual hardware.
> - The "missing" line shows the flags that are present on actual
>   hardware, but not on the added SandyBridge model.
> - The "new" line shows the flags that were not on the Westmere model,
>   but are on SandyBridge.
> 
> feature_edx:
>   Westmere:                 sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge
> mtrr sep apic cx8 mce pae msr tsc pse de     fpu
>   full:        pbe tm ht ss sse2 sse fxsr mmx ds acpi clflush pse36 pat cmov mca
> pge mtrr sep apic cx8 mce pge msr tsc pse de vme fpu
>   SandyBridge:              sse2 sse fxsr mmx         clflush pse36 pat cmov mca pge
> mtrr sep apic cx8 mce pae msr tsc pse de     fpu
>   missing:     pbe tm ht ss                   ds acpi
> vme
> 
> feature_ecx:
>   Westmere:                      aes              popcnt        sse4.2 sse4.1                cx16 ssse3
> sse3
>   full:        avx osxsave xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 pcid
> pdcm xTPR cx16 ssse3 tm2 eist smx vmx ds-cpl monitor dtes64 pclmulqdq
> sse3
>   SandyBridge: avx         xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1
> cx16 ssse3                                        pclmulqdq sse3
>   missing:         osxsave                                                    pcid pdcm xTPR            tm2 eist
> smx vmx ds-cpl monitor dtes64
>   new:         avx         xsave     tsc-deadline        x2apic
> pclmulqdq
> 
> extfeature_edx:
>   Westmere:    i64        nx syscall
>   full:        i64 rdtscp nx syscall
>   SandyBridge: i64 rdtscp nx syscall
>   new:             rdtscp
> 
> extfeature_ecx:
>   Westmere:    lahf_lm
>   full:        lahf_lm
>   SandyBridge: lahf_lm
> 
> Cc: "Dugger, Donald D" <donald.d.dugger@intel.com>
> Cc: "Zhang, Xiantao" <xiantao.zhang@intel.com>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
>  sysconfigs/target/target-x86_64.conf |   14 ++++++++++++++
>  1 files changed, 14 insertions(+), 0 deletions(-)
> 
> diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-
> x86_64.conf
> index d050380..9fecb94 100644
> --- a/sysconfigs/target/target-x86_64.conf
> +++ b/sysconfigs/target/target-x86_64.conf
> @@ -57,6 +57,20 @@
>     model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
> 
>  [cpudef]
> +   name = "SandyBridge"
> +   level = "0xd"
> +   vendor = "GenuineIntel"
> +   family = "6"
> +   model = "42"
> +   stepping = "1"
> +   feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
> sep apic cx8 mce pae msr tsc pse de fpu"
> +   feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1
> cx16 ssse3 pclmulqdq sse3"
> +   extfeature_edx = "i64 rdtscp nx syscall "
> +   extfeature_ecx = "lahf_lm"
> +   xlevel = "0x8000000A"
> +   model_id = "Intel Xeon E312xx (Sandy Bridge)"
> +
> +[cpudef]
>     name = "Opteron_G1"
>     level = "5"
>     vendor = "AuthenticAMD"
> --
> 1.7.3.2

Patch
diff mbox

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index d050380..9fecb94 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -57,6 +57,20 @@ 
    model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
 
 [cpudef]
+   name = "SandyBridge"
+   level = "0xd"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "42"
+   stepping = "1"
+   feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
+   extfeature_edx = "i64 rdtscp nx syscall "
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Intel Xeon E312xx (Sandy Bridge)"
+
+[cpudef]
    name = "Opteron_G1"
    level = "5"
    vendor = "AuthenticAMD"