Patchwork [RFA] PowerPC e5500 and e6500 cores support

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Submitter edmar
Date March 6, 2012, 4:44 p.m.
Message ID <4F563ED8.8090708@freescale.com>
Download mbox | patch
Permalink /patch/144965/
State New
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Comments

edmar - March 6, 2012, 4:44 p.m.
Freescale would like to contribute these patches to gcc.

It enables gcc for the new Freescale 64 bit cores. It creates a pipeline
description,  and set proper default flags for the e5500 and e6500 cores.

Both are 64 bit cores capable to execute popcntb/w/d, bperm, cmpb,
and prtyw/d instructions.

The e6500 core has Altivec and also the new Altivec instructions that
will be part of Power ISA-2.07.
Several tests cases for the new altivec builtins are included.

The patch was generated from subversion revision 184757.

The patch was regression tested for power7 target under these conditions:
--enable-checking --disable-decimal-float --enable-languages=c,c++,fortran

During the development process, an ICE for cell target was found.
The e6500 patch also fixes that problem.

Since the cell ICE is an regression, I have a separate patch and
ChangeLog that can be applied against gcc-4.7/4.6/4.5 to fix this ICE only.
(The branches were also regression tested using the same conditions above)

Regarding the implementation of popcntb, popcntd, and cmpb. Gcc has
dedicated masks on target_flags for them, but due to shortage of bits,
those masks controls more than the name implies.

TARGET_POPCNTB also controls FP reciprocal estimate that the Frescale 
cores does not have
TARGET_POPCNTD also controls FP double word conversion, lfiwzx that the 
Freescale cores does not have.
TARGET_CMPB also controls copy sign, lfiwax that the Freescale cores 
does not have.

In the patch I minimized the number of changes, while not adding
any new mask to target_flags.

A new attribute type "popcnt" is created. This is used in our scheduler,
since it takes 2 cycles on Freescale cores. The scheduler of current
architectures are not affected, because the default value of popcnt type
is the same as not having a type definition on a define_insn.

We thanks in advance for your time to review and commit these patches

Regards,
Edmar

2012-03-01  Edmar Wienskoskiedmar@freescale.com

	* config.gcc (cpu_is_64bit): Add new cores e5500, e6500.
	(powerpc*-*-*): Add new cores e5500, e6500.
	* config/rs6000/rs6000-cpus.def: Add cpu definitions for e5500 and
	e6500.
	* config/rs6000/e5500.md: New file.
	* config/rs6000/e6500.md: New file.
	* config/rs6000/rs6000.opt: Add new option for altivec2.
	* config/rs6000/rs6000-opt.h (processor_type): Add
	PROCESSOR_PPCE5500 and PROCESSOR_PPCE6500.
	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add e5500 and e6500.
	(TARGET_LFIWAX): Exclude e5500 and e6500.
	(TARGET_LFIWZX): Ditto.
	(TARGET_FCFIDS): Re-maps to TARGET_LFIWZX.
	(TARGET_FCFIDU): Ditto.
	(TARGET_FCFIDUS): Ditto.
	(TARGET_FCTIDUZ): Ditto.
	(TARGET_FCTIWUZ): Ditto.
	(TARGET_FRE): Exclude e5500 and e6500.
	(TARGET_FRSQRTES): Ditto.
	(RS6000_BTM_ALTIVEC2): New.
	(RS6000_BTM_COMMON): Add RS6000_BTM_ALTIVEC2.
	* config/rs6000/rs6000.md (define_attr "type"): New type popcnt.
	(define_attr "cpu"): Add ppce5500 and ppce6500.
	Include e5500.md and e6500.md.
	(popcntb<mode>2): Add attribute type popcnt.
	(popcntd<mode>2): Ditto.
	(copysign<mode>3): Re-maps to TARGET_LFIWAX.
	(copysign<mode>3_fcpsgn): Ditto.
	* config/rs6000/rs6000.c (processor_costs): Add new costs for
	e5500 and e6500.
	(POWERPC_MASKS): Add new mask for altivec2.
	(rs6000_builtin_mask_calculate): Add new builtin mask for
	altivec2.
	(rs6000_option_override_internal): Altivec and Spe options not
	allowed with e5500. Spe options not allowed with e6500. Increase
	move inline limit for e5500 and e6500. Disable fsqrt instructions
	for e5500 and e6500. Disable mfocr instruction for e5500. Disable
	string instructions for e5500 and e6500. Enable branch targets
	alignment for e5500 and e6500. Initialize rs6000_cost for e5500
	and e6500.
	(altivec_expand_builtin): Add store vector expansion cases for
	stvexbx, stvexhx, stvexwx, stvflx, stvflxl, stvfrx, stvfrxl,
	stvswx, stvswxl. Add load vector expansion cases for lvexbx,
	lvexhx, lvexwx, lvtlx, lvtlxl, lvtrx, lvtrxl, lvswx, lvswxl, lvsm.
	(altivec_init_builtins): Add builtin and override builtin
	definitions for lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx,
	lvtlx, lvtlxl, lvtrx, lvtrxl, stvflx, stvflxl, stvfrx, stvfrxl,
	lvswx, lvswxl, lvsm, stvswx, stvswxl.
	(builtin_function_type): Set unsigned type flags for vabsdub,
	vabsduh, vabsduw.
	(rs6000_adjust_cost): Add extra scheduling cycles between compare
	and brnach for e5500 and e6500.
	(rs6000_issue_rate): Set issue rate for e5500 and e6500.
	(rs6000_builtin_mask_names): Add entry for altivec2 mask.
	* config/rs6000/altivec.md (unspec): New unspecs: UNSPEC_LVEX,
	UNSPEC_STVEX, UNSPEC_LVTLX, UNSPEC_LVTLXL, UNSPEC_LVTRX,
	UNSPEC_LVTRXL, UNSPEC_STVFLX, UNSPEC_STVFLXL, UNSPEC_STVFRX,
	UNSPEC_STVFRXL, UNSPEC_LVSWX, UNSPEC_LVSWXL, UNSPEC_STVSWX,
	UNSPEC_STVSWXL, UNSPEC_LVSM, UNSPEC_VABSDUB, UNSPEC_VABSDUH,
	UNSPEC_VABSDUW.
	(altivec_vabsduw): New altivec2 insn. Use new unspec.
	(altivec_vabsduh): Ditto.
	(altivec_vabsdub): Ditto.
	(altivec_lvex<VI_char>x): Ditto.
	(altivec_stvex<VI_char>x): Ditto.
	(altivec_lvtlx): Ditto.
	(altivec_lvtlxl): Ditto.
	(altivec_lvtrx): Ditto.
	(altivec_lvtrxl): Ditto.
	(altivec_stvflx): Ditto.
	(altivec_stvflxl): Ditto.
	(altivec_stvfrx): Ditto.
	(altivec_stvfrxl): Ditto.
	(altivec_lvswx): Ditto.
	(altivec_lvswxl): Ditto.
	(altivec_lvsm): Ditto.
	(altivec_stvswx): Ditto.
	(altivec_stvswxl): Ditto.
	(altivec_stvlx): Change machine mode of operands.
	(altivec_stvlxl): Ditto.
	(altivec_stvrx): Ditto.
	(altivec_stvrxl): Ditto.
	* config/rs6000/altivec.h: New altivec2 synonyms.
	* config/rs6000/rs6000-builtin.def: New altivec2 convenience
	macros. Use macros to enter new altivec2 builtin definitions and
	overload builtin definitions for VABSDUB, VABSDUH, VABSDUW,
	LVEXBX, LVEXHX, LVEXWX, LVTLX, LVTLXL, LVTRX, LVTRXL, LVSWX,
	LVSWXL, LVSM, STVEXBX, STVEXHX, STVEXWX, STVFLX, STVFLXL, STVFRX,
	STVFRXL, STVSWX, STVSWXL.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): New
	macro definition for altivec2.
	(altivec_overloaded_builtins): New entries for altivec2 overloads.
	* doc/extend.texi: Document altivec2 builtins.
	* doc/invoke.texi: Add altivec2 PowerPC option.
	(mpopcntb): Document e5500, e6500 implementations.
	(mpopcntd): Document float point conversion instruction and e5500,
	e6500 implementations.
	(mcmpb): Document copy sign instruction and e5500, e6500
	implementations.
	(item -mcpu): Add e5500 and e6500 to list of cpus. Document
	altivec2 PowerPC option.
	(item -maltivec2): New.


2012-03-01  Edmar Wienskoskiedmar@freescale.com

	* gcc.dg/tree-ssa/vector-3.c: Adjust regular expression.
	* gcc.target/powerpc/altivec2_builtin_1.c: New test case.
	* gcc.target/powerpc/altivec2_builtin_2.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_3.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_4.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_5.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_6.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_7.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_8.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_9.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_10.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_11.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_12.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_13.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_14.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_15.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_16.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_17.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_18.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_19.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_20.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_21.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_22.c: Ditto.
	* gcc.target/powerpc/cell_builtin_1.c: Ditto.
	* gcc.target/powerpc/cell_builtin_2.c: Ditto.
	* gcc.target/powerpc/cell_builtin_3.c: Ditto.
	* gcc.target/powerpc/cell_builtin_4.c: Ditto.
	* gcc.target/powerpc/cell_builtin_5.c: Ditto.
	* gcc.target/powerpc/cell_builtin_6.c: Ditto.
	* gcc.target/powerpc/cell_builtin_7.c: Ditto.
	* gcc.target/powerpc/cell_builtin_8.c: Ditto.


ChangeLogs for Cell patch and test cases to be applied on branches 4.7/4.6/4.5

2012-03-01  Edmar Wienskoskiedmar@freescale.com

	* config/rs6000/altivec.md (altivec_stvlx): Change machine mode of
	operands.
	(altivec_stvlxl): Ditto.
	(altivec_stvrx): Ditto.
	(altivec_stvrxl): Ditto.

2012-03-01  Edmar Wienskoskiedmar@freescale.com

	* gcc.target/powerpc/cell_builtin_1.c: Ditto.
	* gcc.target/powerpc/cell_builtin_2.c: Ditto.
	* gcc.target/powerpc/cell_builtin_3.c: Ditto.
	* gcc.target/powerpc/cell_builtin_4.c: Ditto.
	* gcc.target/powerpc/cell_builtin_5.c: Ditto.
	* gcc.target/powerpc/cell_builtin_6.c: Ditto.
	* gcc.target/powerpc/cell_builtin_7.c: Ditto.
	* gcc.target/powerpc/cell_builtin_8.c: Ditto.
2012-03-01  Edmar Wienskoski  edmar@freescale.com

	* config.gcc (cpu_is_64bit): Add new cores e5500, e6500.
	(powerpc*-*-*): Add new cores e5500, e6500.
	* config/rs6000/rs6000-cpus.def: Add cpu definitions for e5500 and
	e6500.
	* config/rs6000/e5500.md: New file.
	* config/rs6000/e6500.md: New file.
	* config/rs6000/rs6000.opt: Add new option for altivec2.
	* config/rs6000/rs6000-opt.h (processor_type): Add
	PROCESSOR_PPCE5500 and PROCESSOR_PPCE6500.
	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add e5500 and e6500.
	(TARGET_LFIWAX): Exclude e5500 and e6500.
	(TARGET_LFIWZX): Ditto.
	(TARGET_FCFIDS): Re-maps to TARGET_LFIWZX.
	(TARGET_FCFIDU): Ditto.
	(TARGET_FCFIDUS): Ditto.
	(TARGET_FCTIDUZ): Ditto.
	(TARGET_FCTIWUZ): Ditto.
	(TARGET_FRE): Exclude e5500 and e6500.
	(TARGET_FRSQRTES): Ditto.
	(RS6000_BTM_ALTIVEC2): New.
	(RS6000_BTM_COMMON): Add RS6000_BTM_ALTIVEC2.
	* config/rs6000/rs6000.md (define_attr "type"): New type popcnt.
	(define_attr "cpu"): Add ppce5500 and ppce6500.
	Include e5500.md and e6500.md.
	(popcntb<mode>2): Add attribute type popcnt.
	(popcntd<mode>2): Ditto.
	(copysign<mode>3): Re-maps to TARGET_LFIWAX.
	(copysign<mode>3_fcpsgn): Ditto.
	* config/rs6000/rs6000.c (processor_costs): Add new costs for
	e5500 and e6500.
	(POWERPC_MASKS): Add new mask for altivec2.
	(rs6000_builtin_mask_calculate): Add new builtin mask for
	altivec2.
	(rs6000_option_override_internal): Altivec and Spe options not
	allowed with e5500. Spe options not allowed with e6500. Increase
	move inline limit for e5500 and e6500. Disable fsqrt instructions
	for e5500 and e6500. Disable mfocr instruction for e5500. Disable
	string instructions for e5500 and e6500. Enable branch targets
	alignment for e5500 and e6500. Initialize rs6000_cost for e5500
	and e6500.
	(altivec_expand_builtin): Add store vector expansion cases for
	stvexbx, stvexhx, stvexwx, stvflx, stvflxl, stvfrx, stvfrxl,
	stvswx, stvswxl. Add load vector expansion cases for lvexbx,
	lvexhx, lvexwx, lvtlx, lvtlxl, lvtrx, lvtrxl, lvswx, lvswxl, lvsm.
	(altivec_init_builtins): Add builtin and override builtin
	definitions for lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx,
	lvtlx, lvtlxl, lvtrx, lvtrxl, stvflx, stvflxl, stvfrx, stvfrxl,
	lvswx, lvswxl, lvsm, stvswx, stvswxl.
	(builtin_function_type): Set unsigned type flags for vabsdub,
	vabsduh, vabsduw.
	(rs6000_adjust_cost): Add extra scheduling cycles between compare
	and brnach for e5500 and e6500.
	(rs6000_issue_rate): Set issue rate for e5500 and e6500.
	(rs6000_builtin_mask_names): Add entry for altivec2 mask.
	* config/rs6000/altivec.md (unspec): New unspecs: UNSPEC_LVEX,
	UNSPEC_STVEX, UNSPEC_LVTLX, UNSPEC_LVTLXL, UNSPEC_LVTRX,
	UNSPEC_LVTRXL, UNSPEC_STVFLX, UNSPEC_STVFLXL, UNSPEC_STVFRX,
	UNSPEC_STVFRXL, UNSPEC_LVSWX, UNSPEC_LVSWXL, UNSPEC_STVSWX,
	UNSPEC_STVSWXL, UNSPEC_LVSM, UNSPEC_VABSDUB, UNSPEC_VABSDUH,
	UNSPEC_VABSDUW.
	(altivec_vabsduw): New altivec2 insn. Use new unspec.
	(altivec_vabsduh): Ditto.
	(altivec_vabsdub): Ditto.
	(altivec_lvex<VI_char>x): Ditto.
	(altivec_stvex<VI_char>x): Ditto.
	(altivec_lvtlx): Ditto.
	(altivec_lvtlxl): Ditto.
	(altivec_lvtrx): Ditto.
	(altivec_lvtrxl): Ditto.
	(altivec_stvflx): Ditto.
	(altivec_stvflxl): Ditto.
	(altivec_stvfrx): Ditto.
	(altivec_stvfrxl): Ditto.
	(altivec_lvswx): Ditto.
	(altivec_lvswxl): Ditto.
	(altivec_lvsm): Ditto.
	(altivec_stvswx): Ditto.
	(altivec_stvswxl): Ditto.
	(altivec_stvlx): Change machine mode of operands.
	(altivec_stvlxl): Ditto.
	(altivec_stvrx): Ditto.
	(altivec_stvrxl): Ditto.
	* config/rs6000/altivec.h: New altivec2 synonyms.
	* config/rs6000/rs6000-builtin.def: New altivec2 convenience
	macros. Use macros to enter new altivec2 builtin definitions and
	overload builtin definitions for VABSDUB, VABSDUH, VABSDUW,
	LVEXBX, LVEXHX, LVEXWX, LVTLX, LVTLXL, LVTRX, LVTRXL, LVSWX,
	LVSWXL, LVSM, STVEXBX, STVEXHX, STVEXWX, STVFLX, STVFLXL, STVFRX,
	STVFRXL, STVSWX, STVSWXL.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): New
	macro definition for altivec2.
	(altivec_overloaded_builtins): New entries for altivec2 overloads.
	* doc/extend.texi: Document altivec2 builtins.
	* doc/invoke.texi: Add altivec2 PowerPC option.
	(mpopcntb): Document e5500, e6500 implementations.
	(mpopcntd): Document float point conversion instruction and e5500,
	e6500 implementations.
	(mcmpb): Document copy sign instruction and e5500, e6500
	implementations.
	(item -mcpu): Add e5500 and e6500 to list of cpus. Document
	altivec2 PowerPC option.
	(item -maltivec2): New.
2012-03-01  Edmar Wienskoski  edmar@freescale.com

	* gcc.dg/tree-ssa/vector-3.c: Adjust regular expression.
	* gcc.target/powerpc/altivec2_builtin_1.c: New test case.
	* gcc.target/powerpc/altivec2_builtin_2.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_3.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_4.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_5.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_6.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_7.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_8.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_9.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_10.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_11.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_12.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_13.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_14.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_15.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_16.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_17.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_18.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_19.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_20.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_21.c: Ditto.
	* gcc.target/powerpc/altivec2_builtin_22.c: Ditto.
	* gcc.target/powerpc/cell_builtin_1.c: Ditto.
	* gcc.target/powerpc/cell_builtin_2.c: Ditto.
	* gcc.target/powerpc/cell_builtin_3.c: Ditto.
	* gcc.target/powerpc/cell_builtin_4.c: Ditto.
	* gcc.target/powerpc/cell_builtin_5.c: Ditto.
	* gcc.target/powerpc/cell_builtin_6.c: Ditto.
	* gcc.target/powerpc/cell_builtin_7.c: Ditto.
	* gcc.target/powerpc/cell_builtin_8.c: Ditto.
2012-03-01  Edmar Wienskoski  edmar@freescale.com

	* config/rs6000/altivec.md (altivec_stvlx): Change machine mode of
	operands.
	(altivec_stvlxl): Ditto.
	(altivec_stvrx): Ditto.
	(altivec_stvrxl): Ditto.
2012-03-01  Edmar Wienskoski  edmar@freescale.com

	* gcc.target/powerpc/cell_builtin_1.c: Ditto.
	* gcc.target/powerpc/cell_builtin_2.c: Ditto.
	* gcc.target/powerpc/cell_builtin_3.c: Ditto.
	* gcc.target/powerpc/cell_builtin_4.c: Ditto.
	* gcc.target/powerpc/cell_builtin_5.c: Ditto.
	* gcc.target/powerpc/cell_builtin_6.c: Ditto.
	* gcc.target/powerpc/cell_builtin_7.c: Ditto.
	* gcc.target/powerpc/cell_builtin_8.c: Ditto.
Michael Meissner - May 17, 2012, 10:16 p.m.
On Tue, Mar 06, 2012 at 11:44:08AM -0500, Edmar wrote:
> Freescale would like to contribute these patches to gcc.
> 
> It enables gcc for the new Freescale 64 bit cores. It creates a pipeline
> description,  and set proper default flags for the e5500 and e6500 cores.
> 
> Both are 64 bit cores capable to execute popcntb/w/d, bperm, cmpb,
> and prtyw/d instructions.
> 
> The e6500 core has Altivec and also the new Altivec instructions that
> will be part of Power ISA-2.07.
> Several tests cases for the new altivec builtins are included.
> 
> The patch was generated from subversion revision 184757.
> 
> The patch was regression tested for power7 target under these conditions:
> --enable-checking --disable-decimal-float --enable-languages=c,c++,fortran
> 
> During the development process, an ICE for cell target was found.
> The e6500 patch also fixes that problem.
> 
> Since the cell ICE is an regression, I have a separate patch and
> ChangeLog that can be applied against gcc-4.7/4.6/4.5 to fix this ICE only.
> (The branches were also regression tested using the same conditions above)
> 
> Regarding the implementation of popcntb, popcntd, and cmpb. Gcc has
> dedicated masks on target_flags for them, but due to shortage of bits,
> those masks controls more than the name implies.
> 
> TARGET_POPCNTB also controls FP reciprocal estimate that the
> Frescale cores does not have
>
> TARGET_POPCNTD also controls FP double word conversion, lfiwzx that
> the Freescale cores does not have.
>
> TARGET_CMPB also controls copy sign, lfiwax that the Freescale cores
> does not have.

As currently used in the compiler:

  * TARGET_POPCNTB is for all insns in ISA 2.04,
  * TARGET_CMPB is for all insns in ISA 2.05 other than Altivec, Decimal
  * TARGET_POPCNTD is for all insns in ISA 2.06 other than Altivec, Decimal,
    and VSX

> In the patch I minimized the number of changes, while not adding
> any new mask to target_flags.

While we may get some bits back when the original Power flags are removed, it
may be time to bite the bullet and have two separate target flags like x86 did,
because we keep running out of bits.

> A new attribute type "popcnt" is created. This is used in our scheduler,
> since it takes 2 cycles on Freescale cores. The scheduler of current
> architectures are not affected, because the default value of popcnt type
> is the same as not having a type definition on a define_insn.

It is 2 cycles on power6/power7 so this is reasonable.

> We thanks in advance for your time to review and commit these patches

Some comments from looking at the patches:

A meta-issue is the name of the Freescale extensions.  The problem of calling
it Altivec2 is we get into a situation like AMD and Intel have had over what
the next SSE revision is.  Perhaps using a different name than Altivec2.  David
probably needs to weigh in on this.

What is the rationale for changing modes for stv* from V4SI to V16QI, and is it
safe?  I'm just worried about existing code, that suddenly stops working.

In rs6000.c, I think gpopt/mfocrf should only be cleared if the user did not
explicitly set those options.  If you want to issue an error if the user
explicitly set the options for the new cpus, that is fine, but I don't like the
backend to silently change options that were explicitly set on the command
line.

In terms of the comments about the insns being in ISA 2.07, that may be
premature until the ISA is actually published.  Also, some of the Altivec2
insns are not in the ISA 2.07 versions I've reviewed (the trouble is finding
which insns are in which RFCs).

I really don't like the explict CPU checks in TARGET_LFIWAX, TARGET_LFIWZX,
because it is easy to miss when the next new cpu comes out.  Perhaps it would
be better to have one more target flag that says to ignore the instructions
Freescale doesn't support.  I dunno, or as I said, maybe it is time to have two
target_flags.  The x86 has also gone to using HOST_WIDE_INT for their two sets
of target flags.

As I mentioned earlier, I like the new popcnt type attribute, but whenever you
add a new type attribute, you should to go through all of the *.md files add
add support for the new attribute.  Now, insns that aren't supported on older
machines are one thing, but since popcnt has been part of the architecture
since the Power/PowerPC came out, I would think you need to edit power4.md,
7xx.md, etc. to add popcnt in the same place as integer.

I think you need to refine the tests, and change powerpc_altivec_ok lines to
something like:
/* { dg-require-effective-target powerpc_altivec2_ok } */

And then add in support in testsuite/lib/target-supports.exp to detect whether
the assembler supports all of the Altivec2 (or whatever we call it)
instructions.  In the same vein, you probably need to add support in
configure.ac to detect whether the assembler knows about the insns similar to
like I did in gcc_cv_as_powerpc_vsx to detect if the assembler knows about
VSX.
edmar - May 18, 2012, 7:16 p.m.
Michael,

Thanks for reviewing the patch and all the suggestions.
I have some questions / comments bellow.

Regards,
Edmar



On 05/17/2012 06:16 PM, Michael Meissner wrote:
>> In the patch I minimized the number of changes, while not adding
>> any new mask to target_flags.
> While we may get some bits back when the original Power flags are removed, it
> may be time to bite the bullet and have two separate target flags like x86 did,
> because we keep running out of bits.
>

I agree. But, wouldn't be better to have the e6500 patch separated from 
this ?
Either way, I would like to collaborate towards having 2 target flags.

> Some comments from looking at the patches:
>
> A meta-issue is the name of the Freescale extensions.  The problem of calling
> it Altivec2 is we get into a situation like AMD and Intel have had over what
> the next SSE revision is.  Perhaps using a different name than Altivec2.  David
> probably needs to weigh in on this.

That name is my fault. Internally Freescale is not giving this feature 
any new name.
Our design manual has a table that lists the differences between the 
original
Altivec and the current Altivec, and that is it.

I thought it would be better to have independent control of the 
instructions,
instead of just throwing everything under __ALTIVEC__
Perhaps we should keep the control that the "-m..." option does and get 
rid of the
  __ALTIVEC2__  definition ?

Regarding the spelling (-maltivec2 or other name), we do not have
any position on it.

> What is the rationale for changing modes for stv* from V4SI to V16QI, and is it
> safe?  I'm just worried about existing code, that suddenly stops working.

Understandable. Right now there is a type mismatch. The RTL is
V4SI and the builtins are emitted with V16QI, causing an ICE.
I traced that ICE all the way back to 4.4.

BTW, the only locations that uses V4SI are the ones I changed...

> In rs6000.c, I think gpopt/mfocrf should only be cleared if the user did not
> explicitly set those options.  If you want to issue an error if the user
> explicitly set the options for the new cpus, that is fine, but I don't like the
> backend to silently change options that were explicitly set on the command
> line.

Thanks for catching this. I will add "target_flags_explicit" to the logic.

> In terms of the comments about the insns being in ISA 2.07, that may be
> premature until the ISA is actually published.  Also, some of the Altivec2
> insns are not in the ISA 2.07 versions I've reviewed (the trouble is finding
> which insns are in which RFCs).

Yes, although we already have silicon out to customers, this is not
a guaranty it will be part of 2.07. I will remove explicit references to 
ISA 2.07.

> I really don't like the explict CPU checks in TARGET_LFIWAX, TARGET_LFIWZX,
> because it is easy to miss when the next new cpu comes out.  Perhaps it would
> be better to have one more target flag that says to ignore the instructions
> Freescale doesn't support.  I dunno, or as I said, maybe it is time to have two
> target_flags.  The x86 has also gone to using HOST_WIDE_INT for their two sets
> of target flags.

I will wait for David on this.

> As I mentioned earlier, I like the new popcnt type attribute, but whenever you
> add a new type attribute, you should to go through all of the *.md files add
> add support for the new attribute.  Now, insns that aren't supported on older
> machines are one thing, but since popcnt has been part of the architecture
> since the Power/PowerPC came out, I would think you need to edit power4.md,
> 7xx.md, etc. to add popcnt in the same place as integer.

The e5500/e6500 are our first parts that does support popcntb/w/d.
And we had manufactured 60x, 7xx, 74xx parts in the past.
Are you sure you want popcnt on 7xx.md ?

So, I have 4xx, a2, power4 through power7. Did I missed any ?

> I think you need to refine the tests, and change powerpc_altivec_ok lines to
> something like:
> /* { dg-require-effective-target powerpc_altivec2_ok } */
>
> And then add in support in testsuite/lib/target-supports.exp to detect whether
> the assembler supports all of the Altivec2 (or whatever we call it)
> instructions.  In the same vein, you probably need to add support in
> configure.ac to detect whether the assembler knows about the insns similar to
> like I did in gcc_cv_as_powerpc_vsx to detect if the assembler knows about
> VSX.

OK, I will work on the changes.
I will follow the name convention when it is decided (altivec2 or 
otherwise).
David Edelsohn - May 21, 2012, 6:51 p.m.
> Regarding the implementation of popcntb, popcntd, and cmpb. Gcc has
> dedicated masks on target_flags for them, but due to shortage of bits,
> those masks controls more than the name implies.

The target flag bits control more than the name implies, but the bits
correspond to published ISA levels.

The Freescale localized parts of the patch (new scheduling
descriptions) are okay, modulo Mike's comments. We also need to
coordinate on which instructions really are part of "Altivec2" and
what name will be used for that feature.


However, what concerns me, as Mike commented as well, is this patch
adds support for a processor that does not conform to any particular
ISA -- it does not implement some instructions and adds other unique
instructions. Unlike the "SPE" instructions, these are not completely
orthogonal from the rest of the PowerPC architecture. SPE added a
separate set of SIMD instructions and merged the GPR and FPR register
sets, but left most other things alone.

The earlier addition of E500 support was a mess because the concept of
architecture and processor were not clearly defined and delineated.
This has been a maintenance nightmare for all other PowerPC
maintainers dealing with the irregularities introduced for Freescale's
non-conforming processor, especially when additional features were
added in the next processor.

At least the previous irregularities were local to Freescale's ISA
extensions. This latest processor modifies the meaning of the ISA
definitions. Changing macros that designate architectures to test for
specific processors is reverting to an approach of bad software
design. If the Freescale parts only has complete support for an
earlier ISA, that is the one it needs to use. If it implements more
"Altivec2" instructions than defined, users can access those with
inlined assembly.

Freescale can distribute compilers with whatever additional patches it
wants to include, but the cost-benefit ratio to the rest of the
PowerPC community and the rest of the GCC community is past
unreasonable.

In other words, this new processor and the latest patches mean that a
Linux distributor cannot build an application for a particular
revision of the ISA and have it work across both IBM and Freescale
processors. That is not the meaning of ISA and is going to confuse
users, developers and distros. The Freescale parts need to present
themselves as the lowest-common denominator of the processor ISA they
supports.

Thanks, David

On Fri, May 18, 2012 at 3:16 PM, Edmar <edmar@freescale.com> wrote:
> Michael,
>
> Thanks for reviewing the patch and all the suggestions.
> I have some questions / comments bellow.
>
> Regards,
> Edmar
>
>
>
> On 05/17/2012 06:16 PM, Michael Meissner wrote:
>>>
>>> In the patch I minimized the number of changes, while not adding
>>> any new mask to target_flags.
>>
>> While we may get some bits back when the original Power flags are removed,
>> it
>> may be time to bite the bullet and have two separate target flags like x86
>> did,
>> because we keep running out of bits.
>>
>
> I agree. But, wouldn't be better to have the e6500 patch separated from this
> ?
> Either way, I would like to collaborate towards having 2 target flags.
>
>> Some comments from looking at the patches:
>>
>> A meta-issue is the name of the Freescale extensions.  The problem of
>> calling
>> it Altivec2 is we get into a situation like AMD and Intel have had over
>> what
>> the next SSE revision is.  Perhaps using a different name than Altivec2.
>>  David
>> probably needs to weigh in on this.
>
>
> That name is my fault. Internally Freescale is not giving this feature any
> new name.
> Our design manual has a table that lists the differences between the
> original
> Altivec and the current Altivec, and that is it.
>
> I thought it would be better to have independent control of the
> instructions,
> instead of just throwing everything under __ALTIVEC__
> Perhaps we should keep the control that the "-m..." option does and get rid
> of the
>  __ALTIVEC2__  definition ?
>
> Regarding the spelling (-maltivec2 or other name), we do not have
> any position on it.
>
>> What is the rationale for changing modes for stv* from V4SI to V16QI, and
>> is it
>> safe?  I'm just worried about existing code, that suddenly stops working.
>
>
> Understandable. Right now there is a type mismatch. The RTL is
> V4SI and the builtins are emitted with V16QI, causing an ICE.
> I traced that ICE all the way back to 4.4.
>
> BTW, the only locations that uses V4SI are the ones I changed...
>
>> In rs6000.c, I think gpopt/mfocrf should only be cleared if the user did
>> not
>> explicitly set those options.  If you want to issue an error if the user
>> explicitly set the options for the new cpus, that is fine, but I don't
>> like the
>> backend to silently change options that were explicitly set on the command
>> line.
>
>
> Thanks for catching this. I will add "target_flags_explicit" to the logic.
>
>> In terms of the comments about the insns being in ISA 2.07, that may be
>> premature until the ISA is actually published.  Also, some of the Altivec2
>> insns are not in the ISA 2.07 versions I've reviewed (the trouble is
>> finding
>> which insns are in which RFCs).
>
>
> Yes, although we already have silicon out to customers, this is not
> a guaranty it will be part of 2.07. I will remove explicit references to ISA
> 2.07.
>
>> I really don't like the explict CPU checks in TARGET_LFIWAX,
>> TARGET_LFIWZX,
>> because it is easy to miss when the next new cpu comes out.  Perhaps it
>> would
>> be better to have one more target flag that says to ignore the
>> instructions
>> Freescale doesn't support.  I dunno, or as I said, maybe it is time to
>> have two
>> target_flags.  The x86 has also gone to using HOST_WIDE_INT for their two
>> sets
>> of target flags.
>
>
> I will wait for David on this.
>
>> As I mentioned earlier, I like the new popcnt type attribute, but whenever
>> you
>> add a new type attribute, you should to go through all of the *.md files
>> add
>> add support for the new attribute.  Now, insns that aren't supported on
>> older
>> machines are one thing, but since popcnt has been part of the architecture
>> since the Power/PowerPC came out, I would think you need to edit
>> power4.md,
>> 7xx.md, etc. to add popcnt in the same place as integer.
>
>
> The e5500/e6500 are our first parts that does support popcntb/w/d.
> And we had manufactured 60x, 7xx, 74xx parts in the past.
> Are you sure you want popcnt on 7xx.md ?
>
> So, I have 4xx, a2, power4 through power7. Did I missed any ?
>
>> I think you need to refine the tests, and change powerpc_altivec_ok lines
>> to
>> something like:
>> /* { dg-require-effective-target powerpc_altivec2_ok } */
>>
>> And then add in support in testsuite/lib/target-supports.exp to detect
>> whether
>> the assembler supports all of the Altivec2 (or whatever we call it)
>> instructions.  In the same vein, you probably need to add support in
>> configure.ac to detect whether the assembler knows about the insns similar
>> to
>> like I did in gcc_cv_as_powerpc_vsx to detect if the assembler knows about
>> VSX.
>
>
> OK, I will work on the changes.
> I will follow the name convention when it is decided (altivec2 or
> otherwise).
>
>
>
>
>
edmar - May 23, 2012, 2:18 p.m.
David, Michael,

Thanks for the feedback.
If you don't object, I will relay the message to the designers.

Meanwhile I have to work with the cards I have, so...
I will break the patch in three parts:
- One that includes the very basic, scheduling etc.
- One for the Altivec builtins, which I will hold until we have a formal
    ISA-2.07 document, and we are sure there is no conflict with the patch.
- The rest that will be kept by Freescale.

Thanks,
Edmar





On 05/21/2012 02:51 PM, David Edelsohn wrote:
>> Regarding the implementation of popcntb, popcntd, and cmpb. Gcc has
>> dedicated masks on target_flags for them, but due to shortage of bits,
>> those masks controls more than the name implies.
> The target flag bits control more than the name implies, but the bits
> correspond to published ISA levels.
>
> The Freescale localized parts of the patch (new scheduling
> descriptions) are okay, modulo Mike's comments. We also need to
> coordinate on which instructions really are part of "Altivec2" and
> what name will be used for that feature.
>
>
> However, what concerns me, as Mike commented as well, is this patch
> adds support for a processor that does not conform to any particular
> ISA -- it does not implement some instructions and adds other unique
> instructions. Unlike the "SPE" instructions, these are not completely
> orthogonal from the rest of the PowerPC architecture. SPE added a
> separate set of SIMD instructions and merged the GPR and FPR register
> sets, but left most other things alone.
>
> The earlier addition of E500 support was a mess because the concept of
> architecture and processor were not clearly defined and delineated.
> This has been a maintenance nightmare for all other PowerPC
> maintainers dealing with the irregularities introduced for Freescale's
> non-conforming processor, especially when additional features were
> added in the next processor.
>
> At least the previous irregularities were local to Freescale's ISA
> extensions. This latest processor modifies the meaning of the ISA
> definitions. Changing macros that designate architectures to test for
> specific processors is reverting to an approach of bad software
> design. If the Freescale parts only has complete support for an
> earlier ISA, that is the one it needs to use. If it implements more
> "Altivec2" instructions than defined, users can access those with
> inlined assembly.
>
> Freescale can distribute compilers with whatever additional patches it
> wants to include, but the cost-benefit ratio to the rest of the
> PowerPC community and the rest of the GCC community is past
> unreasonable.
>
> In other words, this new processor and the latest patches mean that a
> Linux distributor cannot build an application for a particular
> revision of the ISA and have it work across both IBM and Freescale
> processors. That is not the meaning of ISA and is going to confuse
> users, developers and distros. The Freescale parts need to present
> themselves as the lowest-common denominator of the processor ISA they
> supports.
>
> Thanks, David
>
> On Fri, May 18, 2012 at 3:16 PM, Edmar<edmar@freescale.com>  wrote:
>> Michael,
>>
>> Thanks for reviewing the patch and all the suggestions.
>> I have some questions / comments bellow.
>>
>> Regards,
>> Edmar
>>
>>
>>
>> On 05/17/2012 06:16 PM, Michael Meissner wrote:
>>>> In the patch I minimized the number of changes, while not adding
>>>> any new mask to target_flags.
>>> While we may get some bits back when the original Power flags are removed,
>>> it
>>> may be time to bite the bullet and have two separate target flags like x86
>>> did,
>>> because we keep running out of bits.
>>>
>> I agree. But, wouldn't be better to have the e6500 patch separated from this
>> ?
>> Either way, I would like to collaborate towards having 2 target flags.
>>
>>> Some comments from looking at the patches:
>>>
>>> A meta-issue is the name of the Freescale extensions.  The problem of
>>> calling
>>> it Altivec2 is we get into a situation like AMD and Intel have had over
>>> what
>>> the next SSE revision is.  Perhaps using a different name than Altivec2.
>>>   David
>>> probably needs to weigh in on this.
>>
>> That name is my fault. Internally Freescale is not giving this feature any
>> new name.
>> Our design manual has a table that lists the differences between the
>> original
>> Altivec and the current Altivec, and that is it.
>>
>> I thought it would be better to have independent control of the
>> instructions,
>> instead of just throwing everything under __ALTIVEC__
>> Perhaps we should keep the control that the "-m..." option does and get rid
>> of the
>>   __ALTIVEC2__  definition ?
>>
>> Regarding the spelling (-maltivec2 or other name), we do not have
>> any position on it.
>>
>>> What is the rationale for changing modes for stv* from V4SI to V16QI, and
>>> is it
>>> safe?  I'm just worried about existing code, that suddenly stops working.
>>
>> Understandable. Right now there is a type mismatch. The RTL is
>> V4SI and the builtins are emitted with V16QI, causing an ICE.
>> I traced that ICE all the way back to 4.4.
>>
>> BTW, the only locations that uses V4SI are the ones I changed...
>>
>>> In rs6000.c, I think gpopt/mfocrf should only be cleared if the user did
>>> not
>>> explicitly set those options.  If you want to issue an error if the user
>>> explicitly set the options for the new cpus, that is fine, but I don't
>>> like the
>>> backend to silently change options that were explicitly set on the command
>>> line.
>>
>> Thanks for catching this. I will add "target_flags_explicit" to the logic.
>>
>>> In terms of the comments about the insns being in ISA 2.07, that may be
>>> premature until the ISA is actually published.  Also, some of the Altivec2
>>> insns are not in the ISA 2.07 versions I've reviewed (the trouble is
>>> finding
>>> which insns are in which RFCs).
>>
>> Yes, although we already have silicon out to customers, this is not
>> a guaranty it will be part of 2.07. I will remove explicit references to ISA
>> 2.07.
>>
>>> I really don't like the explict CPU checks in TARGET_LFIWAX,
>>> TARGET_LFIWZX,
>>> because it is easy to miss when the next new cpu comes out.  Perhaps it
>>> would
>>> be better to have one more target flag that says to ignore the
>>> instructions
>>> Freescale doesn't support.  I dunno, or as I said, maybe it is time to
>>> have two
>>> target_flags.  The x86 has also gone to using HOST_WIDE_INT for their two
>>> sets
>>> of target flags.
>>
>> I will wait for David on this.
>>
>>> As I mentioned earlier, I like the new popcnt type attribute, but whenever
>>> you
>>> add a new type attribute, you should to go through all of the *.md files
>>> add
>>> add support for the new attribute.  Now, insns that aren't supported on
>>> older
>>> machines are one thing, but since popcnt has been part of the architecture
>>> since the Power/PowerPC came out, I would think you need to edit
>>> power4.md,
>>> 7xx.md, etc. to add popcnt in the same place as integer.
>>
>> The e5500/e6500 are our first parts that does support popcntb/w/d.
>> And we had manufactured 60x, 7xx, 74xx parts in the past.
>> Are you sure you want popcnt on 7xx.md ?
>>
>> So, I have 4xx, a2, power4 through power7. Did I missed any ?
>>
>>> I think you need to refine the tests, and change powerpc_altivec_ok lines
>>> to
>>> something like:
>>> /* { dg-require-effective-target powerpc_altivec2_ok } */
>>>
>>> And then add in support in testsuite/lib/target-supports.exp to detect
>>> whether
>>> the assembler supports all of the Altivec2 (or whatever we call it)
>>> instructions.  In the same vein, you probably need to add support in
>>> configure.ac to detect whether the assembler knows about the insns similar
>>> to
>>> like I did in gcc_cv_as_powerpc_vsx to detect if the assembler knows about
>>> VSX.
>>
>> OK, I will work on the changes.
>> I will follow the name convention when it is decided (altivec2 or
>> otherwise).
>>
>>
>>
>>
>>
> .
>
David Edelsohn - May 23, 2012, 6:33 p.m.
On Wed, May 23, 2012 at 10:18 AM, Edmar <edmar@freescale.com> wrote:
> David, Michael,
>
> Thanks for the feedback.
> If you don't object, I will relay the message to the designers.
>
> Meanwhile I have to work with the cards I have, so...
> I will break the patch in three parts:
> - One that includes the very basic, scheduling etc.
> - One for the Altivec builtins, which I will hold until we have a formal
>   ISA-2.07 document, and we are sure there is no conflict with the patch.
> - The rest that will be kept by Freescale.

Sounds like a reasonable plan. I look forward to your revised patches.

Thanks, David

Patch

diff -ruN gcc-20120223-orig/gcc/config/rs6000/altivec.md gcc-20120223/gcc/config/rs6000/altivec.md
--- gcc-20120223-orig/gcc/config/rs6000/altivec.md	2012-02-23 16:31:51.000000000 -0600
+++ gcc-20120223/gcc/config/rs6000/altivec.md	2012-02-24 13:18:06.612039003 -0600
@@ -2318,8 +2380,8 @@ 
 
 (define_insn "altivec_stvlx"
   [(parallel
-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
-	  (match_operand:V4SI 1 "register_operand" "v"))
+    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+	  (match_operand:V16QI 1 "register_operand" "v"))
      (unspec [(const_int 0)] UNSPEC_STVLX)])]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "stvlx %1,%y0"
@@ -2327,8 +2389,8 @@ 
 
 (define_insn "altivec_stvlxl"
   [(parallel
-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
-	  (match_operand:V4SI 1 "register_operand" "v"))
+    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+	  (match_operand:V16QI 1 "register_operand" "v"))
      (unspec [(const_int 0)] UNSPEC_STVLXL)])]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "stvlxl %1,%y0"
@@ -2336,8 +2398,8 @@ 
 
 (define_insn "altivec_stvrx"
   [(parallel
-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
-	  (match_operand:V4SI 1 "register_operand" "v"))
+    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+	  (match_operand:V16QI 1 "register_operand" "v"))
      (unspec [(const_int 0)] UNSPEC_STVRX)])]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "stvrx %1,%y0"
@@ -2345,8 +2407,8 @@ 
 
 (define_insn "altivec_stvrxl"
   [(parallel
-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
-	  (match_operand:V4SI 1 "register_operand" "v"))
+    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+	  (match_operand:V16QI 1 "register_operand" "v"))
      (unspec [(const_int 0)] UNSPEC_STVRXL)])]
   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
   "stvrxl %1,%y0"
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c	2012-03-01 13:47:03.397039000 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvlx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc1(long a, void *p)           { return __builtin_altivec_lvlx (a,p); }
+vsf  llx01(long a, vsf *p)          { return __builtin_vec_lvlx (a,p); }
+vsf  llx02(long a, sf *p)           { return __builtin_vec_lvlx (a,p); }
+vbi  llx03(long a, vbi *p)          { return __builtin_vec_lvlx (a,p); }
+vsi  llx04(long a, vsi *p)          { return __builtin_vec_lvlx (a,p); }
+vsi  llx05(long a, si *p)           { return __builtin_vec_lvlx (a,p); }
+vui  llx06(long a, vui *p)          { return __builtin_vec_lvlx (a,p); }
+vui  llx07(long a, ui *p)           { return __builtin_vec_lvlx (a,p); }
+vbs  llx08(long a, vbs *p)          { return __builtin_vec_lvlx (a,p); }
+vp   llx09(long a, vp *p)           { return __builtin_vec_lvlx (a,p); }
+vss  llx10(long a, vss *p)          { return __builtin_vec_lvlx (a,p); }
+vss  llx11(long a, ss *p)           { return __builtin_vec_lvlx (a,p); }
+vus  llx12(long a, vus *p)          { return __builtin_vec_lvlx (a,p); }
+vus  llx13(long a, us *p)           { return __builtin_vec_lvlx (a,p); }
+vbc  llx14(long a, vbc *p)          { return __builtin_vec_lvlx (a,p); }
+vsc  llx15(long a, vsc *p)          { return __builtin_vec_lvlx (a,p); }
+vsc  llx16(long a, sc *p)           { return __builtin_vec_lvlx (a,p); }
+vuc  llx17(long a, vuc *p)          { return __builtin_vec_lvlx (a,p); }
+vuc  llx18(long a, uc *p)           { return __builtin_vec_lvlx (a,p); }
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c	2012-03-01 13:47:03.427038997 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvlxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc2(long a, void *p)           { return __builtin_altivec_lvlxl (a,p); }
+vsf  llxl01(long a, vsf *p)         { return __builtin_vec_lvlxl (a,p); }
+vsf  llxl02(long a, sf *p)          { return __builtin_vec_lvlxl (a,p); }
+vbi  llxl03(long a, vbi *p)         { return __builtin_vec_lvlxl (a,p); }
+vsi  llxl04(long a, vsi *p)         { return __builtin_vec_lvlxl (a,p); }
+vsi  llxl05(long a, si *p)          { return __builtin_vec_lvlxl (a,p); }
+vui  llxl06(long a, vui *p)         { return __builtin_vec_lvlxl (a,p); }
+vui  llxl07(long a, ui *p)          { return __builtin_vec_lvlxl (a,p); }
+vbs  llxl08(long a, vbs *p)         { return __builtin_vec_lvlxl (a,p); }
+vp   llxl09(long a, vp *p)          { return __builtin_vec_lvlxl (a,p); }
+vss  llxl10(long a, vss *p)         { return __builtin_vec_lvlxl (a,p); }
+vss  llxl11(long a, ss *p)          { return __builtin_vec_lvlxl (a,p); }
+vus  llxl12(long a, vus *p)         { return __builtin_vec_lvlxl (a,p); }
+vus  llxl13(long a, us *p)          { return __builtin_vec_lvlxl (a,p); }
+vbc  llxl14(long a, vbc *p)         { return __builtin_vec_lvlxl (a,p); }
+vsc  llxl15(long a, vsc *p)         { return __builtin_vec_lvlxl (a,p); }
+vsc  llxl16(long a, sc *p)          { return __builtin_vec_lvlxl (a,p); }
+vuc  llxl17(long a, vuc *p)         { return __builtin_vec_lvlxl (a,p); }
+vuc  llxl18(long a, uc *p)          { return __builtin_vec_lvlxl (a,p); }
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c	2012-03-01 13:47:03.457038951 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvrx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc3(long a, void *p)           { return __builtin_altivec_lvrx (a,p); }
+vsf  lrx01(long a, vsf *p)          { return __builtin_vec_lvrx (a,p); }
+vsf  lrx02(long a, sf *p)           { return __builtin_vec_lvrx (a,p); }
+vbi  lrx03(long a, vbi *p)          { return __builtin_vec_lvrx (a,p); }
+vsi  lrx04(long a, vsi *p)          { return __builtin_vec_lvrx (a,p); }
+vsi  lrx05(long a, si *p)           { return __builtin_vec_lvrx (a,p); }
+vui  lrx06(long a, vui *p)          { return __builtin_vec_lvrx (a,p); }
+vui  lrx07(long a, ui *p)           { return __builtin_vec_lvrx (a,p); }
+vbs  lrx08(long a, vbs *p)          { return __builtin_vec_lvrx (a,p); }
+vp   lrx09(long a, vp *p)           { return __builtin_vec_lvrx (a,p); }
+vss  lrx10(long a, vss *p)          { return __builtin_vec_lvrx (a,p); }
+vss  lrx11(long a, ss *p)           { return __builtin_vec_lvrx (a,p); }
+vus  lrx12(long a, vus *p)          { return __builtin_vec_lvrx (a,p); }
+vus  lrx13(long a, us *p)           { return __builtin_vec_lvrx (a,p); }
+vbc  lrx14(long a, vbc *p)          { return __builtin_vec_lvrx (a,p); }
+vsc  lrx15(long a, vsc *p)          { return __builtin_vec_lvrx (a,p); }
+vsc  lrx16(long a, sc *p)           { return __builtin_vec_lvrx (a,p); }
+vuc  lrx17(long a, vuc *p)          { return __builtin_vec_lvrx (a,p); }
+vuc  lrx18(long a, uc *p)           { return __builtin_vec_lvrx (a,p); }
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c	2012-03-01 13:47:03.487039003 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvrxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc4(long a, void *p)           { return __builtin_altivec_lvrxl (a,p); }
+vsf  lrxl01(long a, vsf *p)         { return __builtin_vec_lvrxl (a,p); }
+vsf  lrxl02(long a, sf *p)          { return __builtin_vec_lvrxl (a,p); }
+vbi  lrxl03(long a, vbi *p)         { return __builtin_vec_lvrxl (a,p); }
+vsi  lrxl04(long a, vsi *p)         { return __builtin_vec_lvrxl (a,p); }
+vsi  lrxl05(long a, si *p)          { return __builtin_vec_lvrxl (a,p); }
+vui  lrxl06(long a, vui *p)         { return __builtin_vec_lvrxl (a,p); }
+vui  lrxl07(long a, ui *p)          { return __builtin_vec_lvrxl (a,p); }
+vbs  lrxl08(long a, vbs *p)         { return __builtin_vec_lvrxl (a,p); }
+vp   lrxl09(long a, vp *p)          { return __builtin_vec_lvrxl (a,p); }
+vss  lrxl10(long a, vss *p)         { return __builtin_vec_lvrxl (a,p); }
+vss  lrxl11(long a, ss *p)          { return __builtin_vec_lvrxl (a,p); }
+vus  lrxl12(long a, vus *p)         { return __builtin_vec_lvrxl (a,p); }
+vus  lrxl13(long a, us *p)          { return __builtin_vec_lvrxl (a,p); }
+vbc  lrxl14(long a, vbc *p)         { return __builtin_vec_lvrxl (a,p); }
+vsc  lrxl15(long a, vsc *p)         { return __builtin_vec_lvrxl (a,p); }
+vsc  lrxl16(long a, sc *p)          { return __builtin_vec_lvrxl (a,p); }
+vuc  lrxl17(long a, vuc *p)         { return __builtin_vec_lvrxl (a,p); }
+vuc  lrxl18(long a, uc *p)          { return __builtin_vec_lvrxl (a,p); }
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c	2012-03-01 13:47:03.517038996 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvlx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc1(vsc v, long a, void *p)    { __builtin_altivec_stvlx (v,a,p); }
+void slx01(vsf v, long a, vsf *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx02(vsf v, long a, sf *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx03(vbi v, long a, vbi *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx04(vsi v, long a, vsi *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx05(vsi v, long a, si *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx06(vui v, long a, vui *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx07(vui v, long a, ui *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx08(vbs v, long a, vbs *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx09(vp v, long a, vp *p)     { __builtin_vec_stvlx (v,a,p); }
+void slx10(vss v, long a, vss *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx11(vss v, long a, ss *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx12(vus v, long a, vus *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx13(vus v, long a, us *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx14(vbc v, long a, vbc *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx15(vsc v, long a, vsc *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx16(vsc v, long a, sc *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx17(vuc v, long a, vuc *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx18(vuc v, long a, uc *p)    { __builtin_vec_stvlx (v,a,p); }
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c	2012-03-01 13:47:03.546038988 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvlxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc2(vsc v, long a, void *p)    { __builtin_altivec_stvlxl (v,a,p); }
+void slxl01(vsf v, long a, vsf *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl02(vsf v, long a, sf *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl03(vbi v, long a, vbi *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl04(vsi v, long a, vsi *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl05(vsi v, long a, si *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl06(vui v, long a, vui *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl07(vui v, long a, ui *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl08(vbs v, long a, vbs *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl09(vp v, long a, vp *p)    { __builtin_vec_stvlxl (v,a,p); }
+void slxl10(vss v, long a, vss *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl11(vss v, long a, ss *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl12(vus v, long a, vus *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl13(vus v, long a, us *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl14(vbc v, long a, vbc *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl15(vsc v, long a, vsc *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl16(vsc v, long a, sc *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl17(vuc v, long a, vuc *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl18(vuc v, long a, uc *p)   { __builtin_vec_stvlxl (v,a,p); }
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c	2012-03-01 13:47:03.577039037 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvrx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc3(vsc v, long a, void *p)    { __builtin_altivec_stvrx (v,a,p); }
+void srx01(vsf v, long a, vsf *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx02(vsf v, long a, sf *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx03(vbi v, long a, vbi *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx04(vsi v, long a, vsi *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx05(vsi v, long a, si *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx06(vui v, long a, vui *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx07(vui v, long a, ui *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx08(vbs v, long a, vbs *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx09(vp v, long a, vp *p)     { __builtin_vec_stvrx (v,a,p); }
+void srx10(vss v, long a, vss *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx11(vss v, long a, ss *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx12(vus v, long a, vus *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx13(vus v, long a, us *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx14(vbc v, long a, vbc *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx15(vsc v, long a, vsc *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx16(vsc v, long a, sc *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx17(vuc v, long a, vuc *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx18(vuc v, long a, uc *p)    { __builtin_vec_stvrx (v,a,p); }
diff -ruN gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c
--- gcc-20120223-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c	1969-12-31 18:00:00.000000000 -0600
+++ gcc-20120223/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c	2012-03-01 13:47:03.607038950 -0600
@@ -0,0 +1,48 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvrxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc4(vsc v, long a, void *p)    { __builtin_altivec_stvrxl (v,a,p); }
+void srxl01(vsf v, long a, vsf *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl02(vsf v, long a, sf *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl03(vbi v, long a, vbi *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl04(vsi v, long a, vsi *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl05(vsi v, long a, si *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl06(vui v, long a, vui *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl07(vui v, long a, ui *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl08(vbs v, long a, vbs *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl09(vp v, long a, vp *p)    { __builtin_vec_stvrxl (v,a,p); }
+void srxl10(vss v, long a, vss *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl11(vss v, long a, ss *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl12(vus v, long a, vus *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl13(vus v, long a, us *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl14(vbc v, long a, vbc *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl15(vsc v, long a, vsc *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl16(vsc v, long a, sc *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl17(vuc v, long a, vuc *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl18(vuc v, long a, uc *p)   { __builtin_vec_stvrxl (v,a,p); }