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Violators will be prosecuted; Mon, 5 Mar 2012 17:23:56 -0700 Received: from d03relay05.boulder.ibm.com (d03relay05.boulder.ibm.com [9.17.195.107]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id E071319D8048 for ; Mon, 5 Mar 2012 17:23:49 -0700 (MST) Received: from d03av05.boulder.ibm.com (d03av05.boulder.ibm.com [9.17.195.85]) by d03relay05.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q260Nrmw212158 for ; Mon, 5 Mar 2012 17:23:53 -0700 Received: from d03av05.boulder.ibm.com (loopback [127.0.0.1]) by d03av05.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q260Nqj3021847 for ; Mon, 5 Mar 2012 17:23:52 -0700 Received: from ibm-tiger.the-meissners.org ([9.33.37.223]) by d03av05.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q260Nq39021811; Mon, 5 Mar 2012 17:23:52 -0700 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id DE73A41377; Mon, 5 Mar 2012 19:23:50 -0500 (EST) Date: Mon, 5 Mar 2012 19:23:50 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, bergner@vnet.ibm.com Subject: [PATCH], PowerPC backend fixes for 50310 (vectorization of IEEE floating point comparisons) Message-ID: <20120306002350.GA26629@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, bergner@vnet.ibm.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12030600-5518-0000-0000-000002BF402B X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On power7 systems, the backend was not prepared to handle vector comparisons with UNEQ, LTGT, ORDERED, and UNORDERED tests, since there is no single comparison instruction for these cases. This patch adds support for doing vector conditional move involving these operations. I have bootstrapped the compiler with these patches, and there were no regressions. The test gcc.c-torture/execute/ieee/pr50340.c now passes if you build the compiler using --with-cpu=power7 as a default (or define ADDITIONAL_TORTURE_OPTIONS in the site.exp file to add -mcpu=power7). Is this ok to install in 4.8? In addition, I would like to backport this fix to the current older branches. Can I check it into the 4.7 branch or should this patch wait until after the 4.7 release for 4.7.1? 2012-03-05 Michael Meissner PR target/50310 * config/rs6000/vector.md (vector_uneq): Add support for UNEQ, LTGT, ORDERED, and UNORDERED IEEE vector comparisons. (vector_ltgt): Likewise. (vector_ordered): Likewise. (vector_unordered): Likewise. * config/rs6000/rs6000.c (rs6000_emit_vector_compare_inner): Likewise. Index: gcc/config/rs6000/vector.md =================================================================== --- gcc/config/rs6000/vector.md (revision 184959) +++ gcc/config/rs6000/vector.md (working copy) @@ -516,6 +516,94 @@ (define_expand "vector_geu" "VECTOR_UNIT_ALTIVEC_P (mode)" "") +(define_insn_and_split "*vector_uneq" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (gt:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (gt:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (not:VEC_F (ior:VEC_F (match_dup 3) + (match_dup 4))))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + +(define_insn_and_split "*vector_ltgt" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (gt:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (gt:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (ior:VEC_F (match_dup 3) + (match_dup 4)))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + +(define_insn_and_split "*vector_ordered" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (ge:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (ge:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (ior:VEC_F (match_dup 3) + (match_dup 4)))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + +(define_insn_and_split "*vector_unordered" + [(set (match_operand:VEC_F 0 "vfloat_operand" "") + (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (match_operand:VEC_F 2 "vfloat_operand" "")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" + "#" + "" + [(set (match_dup 3) + (ge:VEC_F (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (ge:VEC_F (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (not:VEC_F (ior:VEC_F (match_dup 3) + (match_dup 4))))] + " +{ + operands[3] = gen_reg_rtx (mode); + operands[4] = gen_reg_rtx (mode); +}") + ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask ;; which is in the reverse order that we want (define_expand "vector_select_" Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 184959) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -16126,6 +16126,10 @@ rs6000_emit_vector_compare_inner (enum r case EQ: case GT: case GTU: + case ORDERED: + case UNORDERED: + case UNEQ: + case LTGT: mask = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (VOIDmode, mask,