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[58.106.136.119]) by mx.google.com with ESMTPS id h3sm10203123pbr.75.2012.03.04.03.04.20 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 04 Mar 2012 03:04:23 -0800 (PST) From: "Peter A. G. Crosthwaite" To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, john.williams@petalogix.com Date: Sun, 4 Mar 2012 21:03:53 +1000 Message-Id: <2dfabe22de20b5856c06af04ba1c3b9c07b3e554.1330857887.git.peter.crosthwaite@petalogix.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQlAJBN+Z11KyWVITpzlkoj4Ptg1mZz7enS/oE5fZnuFj+tC5mEy6jIlfko0Sd5JE7JPzJsp X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: "Peter A. G. Crosthwaite" , peter.maydell@linaro.org, paul@codesourcery.com Subject: [Qemu-devel] [PATCH v1 3/5] petalogix_s2adsp1800: macro'd magic numbers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Peter A. G. Crosthwaite" defined macros for the addresses of the peripherals in machine model Signed-off-by: Peter A. G. Crosthwaite --- hw/petalogix_s3adsp1800_mmu.c | 20 +++++++++++++------- 1 files changed, 13 insertions(+), 7 deletions(-) diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 99c3590..2cb0b1f 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -42,6 +42,13 @@ #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb" +#define MEMORY_BASEADDR 0x90000000 +#define FLASH_BASEADDR 0xa0000000 +#define INTC_BASEADDR 0x81800000 +#define TIMER_BASEADDR 0x83c00000 +#define UARTLITE_BASEADDR 0x84000000 +#define ETHLITE_BASEADDR 0x81000000 + static void machine_cpu_reset(CPUState *env) { /* FIXME: move to machine specfic cpu reset */ @@ -59,8 +66,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, CPUState *env; DriveInfo *dinfo; int i; - /* FIXME: remove harcoded magic numbers */ - target_phys_addr_t ddr_base = 0x90000000; + target_phys_addr_t ddr_base = MEMORY_BASEADDR; MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32], *cpu_irq; @@ -83,22 +89,22 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, memory_region_add_subregion(sysmem, ddr_base, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(0xa0000000, + pflash_cfi01_register(FLASH_BASEADDR, NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE, dinfo ? dinfo->bdrv : NULL, (64 * 1024), FLASH_SIZE >> 16, 1, 0x89, 0x18, 0x0000, 0x0, 1); cpu_irq = microblaze_pic_init_cpu(env); - dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2); + dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 2); for (i = 0; i < 32; i++) { irq[i] = qdev_get_gpio_in(dev, i); } - sysbus_create_simple("xilinx,uartlite", 0x84000000, irq[3]); + sysbus_create_simple("xilinx,uartlite", UARTLITE_BASEADDR, irq[3]); /* 2 timers at irq 2 @ 62 Mhz. */ - xilinx_timer_create(0x83c00000, irq[0], 2, 62 * 1000000); - xilinx_ethlite_create(&nd_table[0], 0x81000000, irq[1], 0, 0); + xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000); + xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); microblaze_load_kernel(env, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, machine_cpu_reset);