From patchwork Fri Mar 2 12:07:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 144239 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2A783B6F98 for ; Fri, 2 Mar 2012 23:27:09 +1100 (EST) Received: from localhost ([::1]:46970 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3RZj-0006YD-0F for incoming@patchwork.ozlabs.org; Fri, 02 Mar 2012 07:27:07 -0500 Received: from eggs.gnu.org ([208.118.235.92]:60019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3RZX-0006Sy-2J for qemu-devel@nongnu.org; Fri, 02 Mar 2012 07:26:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S3RZC-0006YQ-Ss for qemu-devel@nongnu.org; Fri, 02 Mar 2012 07:26:54 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:39003) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3RZC-0006YI-Kp for qemu-devel@nongnu.org; Fri, 02 Mar 2012 07:26:34 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1S3RGL-0001zG-Ak; Fri, 02 Mar 2012 12:07:05 +0000 From: Peter Maydell To: Anthony Liguori Date: Fri, 2 Mar 2012 12:07:03 +0000 Message-Id: <1330690025-7611-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1330690025-7611-1-git-send-email-peter.maydell@linaro.org> References: <1330690025-7611-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: qemu-devel@nongnu.org, Paul Brook Subject: [Qemu-devel] [PATCH 2/4] arm: make sure that number of irqs can be represented in GICD_TYPER. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Rusty Russell We currently assume that the number of interrupts (ITLinesNumber in the architecture reference manual) is divisible by 32, since we present it to the guest when it reads GICD_TYPER (in gic_dist_readb()) as (N / 32) - 1. Signed-off-by: Rusty Russell Signed-off-by: Peter Maydell --- hw/arm_gic.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 59eabcc..d8a7a19 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -819,6 +819,15 @@ static void gic_init(gic_state *s, int num_irq) hw_error("requested %u interrupt lines exceeds GIC maximum %d\n", num_irq, GIC_MAXIRQ); } + /* ITLinesNumber is represented as (N / 32) - 1 (see + * gic_dist_readb) so this is an implementation imposed + * restriction, not an architectural one: + */ + if (s->num_irq < 32 || (s->num_irq % 32)) { + hw_error("%d interrupt lines unsupported: not divisible by 32\n", + num_irq); + } + qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, s->num_irq - GIC_INTERNAL); for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(&s->busdev, &s->parent_irq[i]);