From patchwork Fri Mar 2 12:20:33 2012
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Subject: [wwwdocs] Detail more ARM-specific changes
From: Richard Earnshaw
X-Patchwork-Id: 144236
Message-Id: <4F50BB11.5050805@arm.com>
To: gcc-patches@gcc.gnu.org, gerald@pfeifer.com
Date: Fri, 02 Mar 2012 12:20:33 +0000
This patch documents some more of the changes that have occurred on ARM
this year. I've also re-worded a couple of the existing changes
recorded there to try and improve the clarity to users.
OK?
Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.94
diff -u -p -r1.94 changes.html
--- changes.html 2 Mar 2012 09:53:07 -0000 1.94
+++ changes.html 2 Mar 2012 12:16:39 -0000
@@ -618,15 +618,32 @@ well.
ARM
- - GCC now supports the Cortex-A7 processor implementing the
- v7-a version of the architecture using the option
+
- GCC now supports the Cortex-A7 processor, implementing the
+ ARMv7-A version of the architecture, using the option
-mcpu=cortex-a7.
- - The default vector size in auto-vectorization for NEON is now 128 bits.
- If vectorization fails thusly, the vectorizer tries again with
- 64-bit vectors.
+ - GCC now supports the Cortex-R5 processor, implementing the
+ ARMv7-R version of the architecture, using the option
+
-mcpu=cortex-r5.
+ - GCC can now automatically detect the host
+ processor during native compilation. The options
+
-mcpu=, -mtune= and
+ -march= now all accept native in place of
+ the architecture or processor name.
+ - The default vector size in auto-vectorization for NEON is now
+ 128 bits. If vectorization with 128-bit vectors fails, the vectorizer
+ will try again with 64-bit vectors.
- A new option
-mvectorize-with-neon-double was added to
- allow users to change the vector size to 64 bits.
-
+ restrict auto-vectorization to using 64-bit vectors.
+ - A number of improvements have been made around code generation for
+ the strided loads and stores for the Neon Advanced SIMD extension.
+ The auto-vectorizer and the backend now fully support the strided load
+ and store instructions (for example vld3 and vld4).
+ - Code generation for the Cortex-A15 processor has been improved.
+ - 64-bit sync primitives are now supported on ARM.
+ Note that code generated for cores implementing architectures prior
+ to ARMv7 will normally need support from kernel helper functions;
+ on Linux, kernel versions 3.1 and later provide the required
+ support.
AVR