From patchwork Thu Mar 1 05:54:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [1] invoke.texi : Document AMD bdver2 Date: Wed, 29 Feb 2012 19:54:10 -0000 From: venkataramanan.kumar@amd.com X-Patchwork-Id: 143910 Message-Id: <7794A52CE4D579448B959EED7DD0A47204230717@sausexdag03.amd.com> To: "gcc-patches@gcc.gnu.org" Cc: "gerald@pfeifer.com" , "ubizjak@gmail.com" , "rguenther@suse.de" , "Neill, Quentin" Hi Maintainers, We want to add bdver2 description in invoke.texi for GCC 4.7. Here is the patch that does that. Ok for trunk ? Can I commit in trunk so that it gets picked up for GCC 4.7? Regards, Venkat. Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 183891) +++ gcc/doc/invoke.texi (working copy) @@ -13063,8 +13063,12 @@ @item bdver1 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, -SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit -instruction set extensions.) +SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) +@item bdver2 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, +SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set +extensions.) @item btver1 AMD Family 14h core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit Index: gcc/ChangeLog =================================================================== --- gcc/ChangeLog (revision 183891) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,6 @@ +2012-03-01 Venkataramanan Kumar + * doc/invoke.texi: Document AMD bdver2 and remove mentioning 3DNow from bdver1. + 2012-02-03 Jakub Jelinek Zdenek Dvorak