Patchwork [1] invoke.texi : Document AMD bdver2

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Submitter venkataramanan.kumar@amd.com
Date March 1, 2012, 5:54 a.m.
Message ID <7794A52CE4D579448B959EED7DD0A47204230717@sausexdag03.amd.com>
Download mbox | patch
Permalink /patch/143910/
State New
Headers show

Comments

venkataramanan.kumar@amd.com - March 1, 2012, 5:54 a.m.
Hi Maintainers,

We want to add bdver2 description in invoke.texi for GCC 4.7. Here is the patch that does that.

Ok for trunk ? 

Can I commit in trunk so that it gets picked up for GCC 4.7?

Regards,
Venkat.
Richard Guenther - March 1, 2012, 9:24 a.m.
On Thu, 1 Mar 2012, Kumar, Venkataramanan wrote:

> Hi Maintainers,
> 
> We want to add bdver2 description in invoke.texi for GCC 4.7. Here is the patch that does that.
> 
> Index: gcc/doc/invoke.texi
> ===================================================================
> --- gcc/doc/invoke.texi (revision 183891)
> +++ gcc/doc/invoke.texi (working copy)
> @@ -13063,8 +13063,12 @@
>  @item bdver1
>  AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
>  supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
> -SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
> -instruction set extensions.)
> +SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
> +@item bdver2
> +AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
> +supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE,
> +SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
> +extensions.)
>  @item btver1
>  AMD Family 14h core based CPUs with x86-64 instruction set support.  (This
>  supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
> 
> Index: gcc/ChangeLog
> ===================================================================
> --- gcc/ChangeLog       (revision 183891)
> +++ gcc/ChangeLog       (working copy)
> @@ -1,3 +1,6 @@
> +2012-03-01  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
> +       * doc/invoke.texi: Document AMD bdver2 and remove mentioning 3DNow from bdver1.
> +
>  2012-02-03  Jakub Jelinek  <jakub@redhat.com>
>             Zdenek Dvorak  <ook@ucw.cz>
> 
> Ok for trunk ? 

Ok, but please watch formatting of the ChangeLog entry, you miss a newline
before * doc/invoke.texi

Thanks,
Richard.

> Can I commit in trunk so that it gets picked up for GCC 4.7?
> 
> Regards,
> Venkat.
> 
>
venkataramanan.kumar@amd.com - March 1, 2012, 9:59 a.m.
Thanks Richard.

I have committed the patch and taken care of new line as well.

Regards,
Venkat.

> -----Original Message-----
> From: Richard Guenther [mailto:rguenther@suse.de]
> Sent: Thursday, March 01, 2012 2:55 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org; gerald@pfeifer.com; ubizjak@gmail.com; Neill,
> Quentin
> Subject: Re: [Patch 1] invoke.texi : Document AMD bdver2
> 
> On Thu, 1 Mar 2012, Kumar, Venkataramanan wrote:
> 
> > Hi Maintainers,
> >
> > We want to add bdver2 description in invoke.texi for GCC 4.7. Here is the
> patch that does that.
> >
> > Index: gcc/doc/invoke.texi
> > ===================================================================
> > --- gcc/doc/invoke.texi (revision 183891)
> > +++ gcc/doc/invoke.texi (working copy)
> > @@ -13063,8 +13063,12 @@
> >  @item bdver1
> >  AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
> >  supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3,
> SSE4A,
> > -SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
> > -instruction set extensions.)
> > +SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
> > +@item bdver2
> > +AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
> > +supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE,
> > +SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
> > +extensions.)
> >  @item btver1
> >  AMD Family 14h core based CPUs with x86-64 instruction set support.  (This
> >  supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
> >
> > Index: gcc/ChangeLog
> > ===================================================================
> > --- gcc/ChangeLog       (revision 183891)
> > +++ gcc/ChangeLog       (working copy)
> > @@ -1,3 +1,6 @@
> > +2012-03-01  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
> > +       * doc/invoke.texi: Document AMD bdver2 and remove mentioning 3DNow
> from bdver1.
> > +
> >  2012-02-03  Jakub Jelinek  <jakub@redhat.com>
> >             Zdenek Dvorak  <ook@ucw.cz>
> >
> > Ok for trunk ?
> 
> Ok, but please watch formatting of the ChangeLog entry, you miss a newline
> before * doc/invoke.texi
> 
> Thanks,
> Richard.
> 
> > Can I commit in trunk so that it gets picked up for GCC 4.7?
> >
> > Regards,
> > Venkat.
> >
> >
> 
> --
> Richard Guenther <rguenther@suse.de>
> SUSE / SUSE Labs
> SUSE LINUX Products GmbH - Nuernberg - AG Nuernberg - HRB 16746
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer

Patch

Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 183891)
+++ gcc/doc/invoke.texi (working copy)
@@ -13063,8 +13063,12 @@ 
 @item bdver1
 AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
 supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
-SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
-instruction set extensions.)
+SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
+@item bdver2
+AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
+supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE,
+SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
+extensions.)
 @item btver1
 AMD Family 14h core based CPUs with x86-64 instruction set support.  (This
 supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit

Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog       (revision 183891)
+++ gcc/ChangeLog       (working copy)
@@ -1,3 +1,6 @@ 
+2012-03-01  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+       * doc/invoke.texi: Document AMD bdver2 and remove mentioning 3DNow from bdver1.
+
 2012-02-03  Jakub Jelinek  <jakub@redhat.com>
            Zdenek Dvorak  <ook@ucw.cz>