From patchwork Tue Feb 28 18:07:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 143529 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id ADA39B6FA8 for ; Wed, 29 Feb 2012 05:10:03 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A9174280D5; Tue, 28 Feb 2012 19:09:51 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hU0tFk20xRvq; Tue, 28 Feb 2012 19:09:51 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 69CC6280C9; Tue, 28 Feb 2012 19:09:43 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F1D99280B2 for ; Tue, 28 Feb 2012 19:09:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eCxeU2HnHpVP for ; Tue, 28 Feb 2012 19:09:37 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ey0-f202.google.com (mail-ey0-f202.google.com [209.85.215.202]) by theia.denx.de (Postfix) with ESMTPS id 182AB280C3 for ; Tue, 28 Feb 2012 19:09:32 +0100 (CET) Received: by eaaq10 with SMTP id q10so25642eaa.3 for ; Tue, 28 Feb 2012 10:09:30 -0800 (PST) Received-SPF: pass (google.com: domain of sjg@google.com designates 10.14.29.144 as permitted sender) client-ip=10.14.29.144; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sjg@google.com designates 10.14.29.144 as permitted sender) smtp.mail=sjg@google.com Received: from mr.google.com ([10.14.29.144]) by 10.14.29.144 with SMTP id i16mr8867167eea.4.1330452570568 (num_hops = 1); Tue, 28 Feb 2012 10:09:30 -0800 (PST) Received: by 10.14.29.144 with SMTP id i16mr7729892eea.4.1330452570555; Tue, 28 Feb 2012 10:09:30 -0800 (PST) MIME-Version: 1.0 Received: by 10.14.29.144 with SMTP id i16mr7729858eea.4.1330452570377; Tue, 28 Feb 2012 10:09:30 -0800 (PST) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id n48si14128242eeh.1.2012.02.28.10.09.30 (version=TLSv1/SSLv3 cipher=AES128-SHA); Tue, 28 Feb 2012 10:09:30 -0800 (PST) Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id EB99320004E; Tue, 28 Feb 2012 10:09:29 -0800 (PST) Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id 5C0DB14094B; Tue, 28 Feb 2012 10:09:29 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Tue, 28 Feb 2012 10:07:53 -0800 Message-Id: <1330452478-5039-16-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1330452478-5039-10-git-send-email-sjg@chromium.org> References: <1330452478-5039-10-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQlIGxAQCxhFCtl06x1ipM+Dp/faC4SIx8FWgWeZjxuILtYcJ9cY2opxKEkl7+xfhej8nvUgExzgB2CkGQs3aq0i3weJUFRtiqMZq07cf/19yJ+eSP09TsZPqwb+iTLDHFrQlw9hKS/pneA9wxNv3/VMN16PH+K8vO3G3+Ya5wjL3bq/Ggk= Cc: Devicetree Discuss , Jerry Van Baren , Tom Warren , linux-tegra@vger.kernel.org Subject: [U-Boot] [PATCH v7 15/20] tegra: fdt: Add function to return peripheral/clock ID X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself). Signed-off-by: Simon Glass Acked-by: Stephen Warren --- Changes in v4: - Add fdtdec function to return peripheral ID Changes in v6: - Move peripheral decode function into Tegra's clock.c Changes in v7: - Add belts and braces checking of device tree clock ID arch/arm/cpu/armv7/tegra2/clock.c | 56 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/clock.h | 13 +++++++ 2 files changed, 69 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 11d2346..959322b 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -28,6 +28,7 @@ #include #include #include +#include /* * This is our record of the current clock rate of each clock. We don't @@ -918,6 +919,61 @@ void clock_ll_start_uart(enum periph_id periph_id) reset_set_enable(periph_id, 0); } +/* + * Convert a device tree clock ID to our peripheral ID. They are mostly + * the same but we are very cautious so we check that a valid clock ID is + * provided. + * + * @param clk_id Clock ID according to tegra2 device tree binding + * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + */ +static enum periph_id clk_id_to_periph_id(int clk_id) +{ + if (clk_id > 95) + return PERIPH_ID_NONE; + + switch (clk_id) { + case 1: + case 2: + case 7: + case 10: + case 20: + case 30: + case 35: + case 49: + case 56: + case 74: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 91: + case 95: + return PERIPH_ID_NONE; + default: + return clk_id; + } +} + +int clock_decode_periph_id(const void *blob, int node) +{ + enum periph_id id; + u32 cell[2]; + int err; + + err = fdtdec_get_int_array(blob, node, "clocks", cell, + ARRAY_SIZE(cell)); + if (err) + return -1; + id = clk_id_to_periph_id(cell[1]); + assert(clock_periph_id_isvalid(id)); + return id; +} + int clock_verify(void) { struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 080ef18..6b12c76 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -177,6 +177,7 @@ enum periph_id { PERIPH_ID_CRAM2, PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, }; /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ @@ -355,6 +356,18 @@ unsigned clock_get_rate(enum clock_id clkid); */ void clock_ll_start_uart(enum periph_id periph_id); +/** + * Decode a peripheral ID from a device tree node. + * + * This works by looking up the peripheral's 'clocks' node and reading out + * the second cell, which is the clock number / peripheral ID. + * + * @param blob FDT blob to use + * @param node Node to look at + * @return peripheral ID, or PERIPH_ID_NONE if none + */ +enum periph_id clock_decode_periph_id(const void *blob, int node); + /* * Checks that clocks are valid and prints a warning if not *