From patchwork Tue Feb 28 05:15:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 143363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 57A94B6FA5 for ; Tue, 28 Feb 2012 18:26:10 +1100 (EST) Received: from localhost ([::1]:54462 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2HRn-00036d-ND for incoming@patchwork.ozlabs.org; Tue, 28 Feb 2012 02:26:07 -0500 Received: from eggs.gnu.org ([208.118.235.92]:60718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2FQz-0000wr-8T for qemu-devel@nongnu.org; Tue, 28 Feb 2012 00:17:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S2FQx-0002q8-9U for qemu-devel@nongnu.org; Tue, 28 Feb 2012 00:17:08 -0500 Received: from mga09.intel.com ([134.134.136.24]:21943) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2FQw-0002po-Sc for qemu-devel@nongnu.org; Tue, 28 Feb 2012 00:17:07 -0500 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 27 Feb 2012 21:17:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.67,352,1309762800"; d="scan'208,223";a="112485281" Received: from pgsmsx101.gar.corp.intel.com ([10.221.44.78]) by orsmga001.jf.intel.com with ESMTP; 27 Feb 2012 21:16:00 -0800 Received: from pgsmsx152.gar.corp.intel.com (172.30.236.43) by PGSMSX101.gar.corp.intel.com (10.221.44.78) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 28 Feb 2012 13:15:47 +0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by PGSMSX152.gar.corp.intel.com (172.30.236.43) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 28 Feb 2012 13:15:47 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.142]) by SHSMSX102.ccr.corp.intel.com ([169.254.2.36]) with mapi id 14.01.0355.002; Tue, 28 Feb 2012 13:15:47 +0800 From: "Liu, Jinsong" To: Avi Kivity , Marcelo Tosatti , kvm Thread-Topic: [PATCH] KVM: expose Intel cpu new features to guest Thread-Index: Acz12AfD+C1/GVRETrC6QVacSYHMZQ== Date: Tue, 28 Feb 2012 05:15:46 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 X-Mailman-Approved-At: Tue, 28 Feb 2012 02:25:57 -0500 Cc: Jan Kiszka , "qemu-devel@nongnu.org" Subject: [Qemu-devel] [PATCH] KVM: expose Intel cpu new features to guest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From ecd8be962f69393c183f941bfdbd7a7d3876d442 Mon Sep 17 00:00:00 2001 From: Liu, Jinsong Date: Mon, 27 Feb 2012 05:19:32 +0800 Subject: [PATCH] KVM: expose Intel cpu new features to guest Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to guest. Signed-off-by: Liu, Jinsong --- arch/x86/include/asm/cpufeature.h | 2 ++ arch/x86/kvm/cpuid.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 17c5d4b..e8d12a8 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -198,10 +198,12 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ #define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ #define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ +#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ #define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ #define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ +#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ #if defined(__KERNEL__) && !defined(__ASSEMBLY__) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 9fed5be..c2134b8 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -247,7 +247,8 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, /* cpuid 7.0.ebx */ const u32 kvm_supported_word9_x86_features = - F(FSGSBASE) | F(BMI1) | F(AVX2) | F(SMEP) | F(BMI2) | F(ERMS); + F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | + F(BMI2) | F(ERMS) | F(RTM); /* all calls to cpuid_count() should be made on the same cpu */ get_cpu();