From patchwork Mon Feb 27 20:52:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 143278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5AB47B6EEC for ; Tue, 28 Feb 2012 07:55:04 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3975728378; Mon, 27 Feb 2012 21:54:44 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oEQD-qbMqrsy; Mon, 27 Feb 2012 21:54:43 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 609432832E; Mon, 27 Feb 2012 21:53:55 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 84F6F2833B for ; Mon, 27 Feb 2012 21:53:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lItqRjYY+maX for ; Mon, 27 Feb 2012 21:53:26 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-we0-f202.google.com (mail-we0-f202.google.com [74.125.82.202]) by theia.denx.de (Postfix) with ESMTPS id 3FECB2833E for ; Mon, 27 Feb 2012 21:53:23 +0100 (CET) Received: by wejx9 with SMTP id x9so35949wej.3 for ; Mon, 27 Feb 2012 12:53:22 -0800 (PST) Received-SPF: pass (google.com: domain of sjg@google.com designates 10.14.200.200 as permitted sender) client-ip=10.14.200.200; Authentication-Results: mr.google.com; spf=pass (google.com: domain of sjg@google.com designates 10.14.200.200 as permitted sender) smtp.mail=sjg@google.com Received: from mr.google.com ([10.14.200.200]) by 10.14.200.200 with SMTP id z48mr5365169een.6.1330376002003 (num_hops = 1); Mon, 27 Feb 2012 12:53:22 -0800 (PST) Received: by 10.14.200.200 with SMTP id z48mr4766191een.6.1330376001996; Mon, 27 Feb 2012 12:53:21 -0800 (PST) MIME-Version: 1.0 Received: by 10.14.200.200 with SMTP id z48mr4766168een.6.1330376001907; Mon, 27 Feb 2012 12:53:21 -0800 (PST) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id n48si11832287eeh.1.2012.02.27.12.53.21 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 27 Feb 2012 12:53:21 -0800 (PST) Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id 8D0BC200057; Mon, 27 Feb 2012 12:53:21 -0800 (PST) Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id E70B1146F9F; Mon, 27 Feb 2012 12:53:20 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 27 Feb 2012 12:52:38 -0800 Message-Id: <1330375973-10681-6-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1330375973-10681-1-git-send-email-sjg@chromium.org> References: <1330375973-10681-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQkp4LKh0eFiDH74sVLT782pDMoC+Ki6EEko4tSFW+M6VtsQkXq/x6QjiSyC4iE3TIIXMANMveY63ud6pCbTyxJ9FHua1K9MmEGNSlr5kpCkgr4fAmc9i1Gv82SfscnXkqnOZhrBJgEr2Yj7bkSeOTCsyzQx9+AFdoBS7+/XqwC6jEAWaRw= Cc: Devicetree Discuss , Jerry Van Baren , Tom Warren , linux-tegra@vger.kernel.org Subject: [U-Boot] [PATCH v6 05/20] tegra: fdt: Add Tegra2x device tree file from kernel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git config.mk is updated to provide this file to boards through the built-in mechanism: /include/ ARCH_CPU_DTS Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra2/config.mk | 2 + arch/arm/dts/tegra20.dtsi | 168 +++++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+), 0 deletions(-) create mode 100644 arch/arm/dts/tegra20.dtsi diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index 2303dba..fe9ef5b 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -31,3 +31,5 @@ CFLAGS_arch/arm/lib/board.o += -march=armv4t endif USE_PRIVATE_LIBGCC = yes + +CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi new file mode 100644 index 0000000..a9a98ea --- /dev/null +++ b/arch/arm/dts/tegra20.dtsi @@ -0,0 +1,168 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra20"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "nvidia,tegra20-gic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 70 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 124 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x200>; + interrupts = < 85 >; + }; + + i2s@70002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = < 45 >; + dma-channel = < 2 >; + }; + + i2s@70002a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = < 35 >; + dma-channel = < 1 >; + }; + + das@70000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 64 65 66 67 87 119 121 >; + #gpio-cells = <2>; + gpio-controller; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8 >; /* Pad control registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 68 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 69 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 78 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 122 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 123 >; + }; + + sdhci@c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = < 46 >; + }; + + sdhci@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = < 47 >; + }; + + sdhci@c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = < 51 >; + }; + + sdhci@c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = < 63 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 53 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + }; + +};