From patchwork Sun Feb 26 23:01:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 143131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 37A47B6FC4 for ; Mon, 27 Feb 2012 10:02:22 +1100 (EST) Received: from localhost ([::1]:47005 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S1n6g-0004UQ-Nu for incoming@patchwork.ozlabs.org; Sun, 26 Feb 2012 18:02:18 -0500 Received: from eggs.gnu.org ([208.118.235.92]:45207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S1n6Z-0004UH-8d for qemu-devel@nongnu.org; Sun, 26 Feb 2012 18:02:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S1n6X-0000fa-3L for qemu-devel@nongnu.org; Sun, 26 Feb 2012 18:02:11 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:40056) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S1n6W-0000fE-GX for qemu-devel@nongnu.org; Sun, 26 Feb 2012 18:02:09 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1S1n6K-00088z-Kh; Sun, 26 Feb 2012 23:01:56 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Sun, 26 Feb 2012 23:01:56 +0000 Message-Id: <1330297316-31282-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Riku Voipio , =?UTF-8?q?Juha=20Riihim=C3=A4ki?= , patches@linaro.org Subject: [Qemu-devel] [PATCH] hw/omap_i2c: Convert to qdev X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Juha Riihimäki Convert the omap_i2c device to qdev. Signed-off-by: Juha Riihimäki [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell --- This isn't the only omap_i2c patch I have in my tree (there's a lot of omap3 support that still needs untangling) but I think this change make sense on its own, so here it is. hw/nseries.c | 12 +++---- hw/omap.h | 13 +------ hw/omap1.c | 13 +++++-- hw/omap2.c | 35 ++++++++++++------ hw/omap_i2c.c | 107 +++++++++++++++++++++++++++++++++------------------------ 5 files changed, 101 insertions(+), 79 deletions(-) diff --git a/hw/nseries.c b/hw/nseries.c index c5b3184..a5cfa8c 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -45,7 +45,6 @@ struct n800_s { uint32_t (*txrx)(void *opaque, uint32_t value, int len); uWireSlave *chip; } ts; - i2c_bus *i2c; int keymap[0x80]; DeviceState *kbd; @@ -194,12 +193,10 @@ static void n8x0_i2c_setup(struct n800_s *s) { DeviceState *dev; qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO); - - /* Attach the CPU on one end of our I2C bus. */ - s->i2c = omap_i2c_bus(s->cpu->i2c[0]); + i2c_bus *i2c = omap_i2c_bus(s->cpu->i2c[0]); /* Attach a menelaus PM chip */ - dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR); + dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR); qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(s->cpu->ih[0], OMAP_INT_24XX_SYS_NIRQ)); @@ -207,7 +204,7 @@ static void n8x0_i2c_setup(struct n800_s *s) qemu_system_powerdown = qdev_get_gpio_in(dev, 3); /* Attach a TMP105 PM chip (A0 wired to ground) */ - dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR); + dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR); qdev_connect_gpio_out(dev, 0, tmp_irq); } @@ -391,7 +388,8 @@ static void n810_kbd_setup(struct n800_s *s) /* Attach the LM8322 keyboard to the I2C bus, * should happen in n8x0_i2c_setup and s->kbd be initialised here. */ - s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR); + s->kbd = i2c_create_slave(omap_i2c_bus(s->cpu->i2c[0]), + "lm8323", N810_LM8323_ADDR); qdev_connect_gpio_out(s->kbd, 0, kbd_irq); } diff --git a/hw/omap.h b/hw/omap.h index 60fa34c..49ff0bf 100644 --- a/hw/omap.h +++ b/hw/omap.h @@ -764,16 +764,7 @@ void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); void omap_mmc_enable(struct omap_mmc_s *s, int enable); /* omap_i2c.c */ -struct omap_i2c_s; -struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem, - target_phys_addr_t base, - qemu_irq irq, - qemu_irq *dma, - omap_clk clk); -struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, - qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); -void omap_i2c_reset(struct omap_i2c_s *s); -i2c_bus *omap_i2c_bus(struct omap_i2c_s *s); +i2c_bus *omap_i2c_bus(DeviceState *omap_i2c); # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) @@ -867,7 +858,7 @@ struct omap_mpu_state_s { struct omap_pwl_s *pwl; struct omap_pwt_s *pwt; - struct omap_i2c_s *i2c[2]; + DeviceState *i2c[2]; struct omap_rtc_s *rtc; diff --git a/hw/omap1.c b/hw/omap1.c index 1aa5f23..3d8e7ab 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -3694,7 +3694,6 @@ static void omap1_mpu_reset(void *opaque) omap_uwire_reset(mpu->microwire); omap_pwl_reset(mpu->pwl); omap_pwt_reset(mpu->pwt); - omap_i2c_reset(mpu->i2c[0]); omap_rtc_reset(mpu->rtc); omap_mcbsp_reset(mpu->mcbsp1); omap_mcbsp_reset(mpu->mcbsp2); @@ -3993,9 +3992,15 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, s->pwt = omap_pwt_init(system_memory, 0xfffb6000, omap_findclk(s, "armxor_ck")); - s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800, - qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C), - &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck")); + s->i2c[0] = qdev_create(NULL, "omap_i2c"); + qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); + qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); + qdev_init_nofail(s->i2c[0]); + busdev = sysbus_from_qdev(s->i2c[0]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); + sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); + sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); + sysbus_mmio_map(busdev, 0, 0xfffb3800); s->rtc = omap_rtc_init(system_memory, 0xfffb4800, qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), diff --git a/hw/omap2.c b/hw/omap2.c index a6851b0..5689c70 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -2222,8 +2222,6 @@ static void omap2_mpu_reset(void *opaque) omap_mmc_reset(mpu->mmc); omap_mcspi_reset(mpu->mcspi[0]); omap_mcspi_reset(mpu->mcspi[1]); - omap_i2c_reset(mpu->i2c[0]); - omap_i2c_reset(mpu->i2c[1]); cpu_reset(mpu->env); } @@ -2395,16 +2393,29 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, omap_findclk(s, "clk32-kHz"), omap_findclk(s, "core_l4_iclk")); - s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5), - qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ), - &s->drq[OMAP24XX_DMA_I2C1_TX], - omap_findclk(s, "i2c1.fclk"), - omap_findclk(s, "i2c1.iclk")); - s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6), - qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ), - &s->drq[OMAP24XX_DMA_I2C2_TX], - omap_findclk(s, "i2c2.fclk"), - omap_findclk(s, "i2c2.iclk")); + s->i2c[0] = qdev_create(NULL, "omap_i2c"); + qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); + qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk")); + qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk")); + qdev_init_nofail(s->i2c[0]); + busdev = sysbus_from_qdev(s->i2c[0]); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ)); + sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]); + sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]); + sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0)); + + s->i2c[1] = qdev_create(NULL, "omap_i2c"); + qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); + qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk")); + qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk")); + qdev_init_nofail(s->i2c[1]); + busdev = sysbus_from_qdev(s->i2c[1]); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ)); + sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]); + sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]); + sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0)); s->gpio = qdev_create(NULL, "omap2-gpio"); qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c index 5ec422c..20bc82e 100644 --- a/hw/omap_i2c.c +++ b/hw/omap_i2c.c @@ -19,14 +19,20 @@ #include "hw.h" #include "i2c.h" #include "omap.h" +#include "sysbus.h" -struct omap_i2c_s { + +typedef struct OMAPI2CState { + SysBusDevice busdev; MemoryRegion iomem; qemu_irq irq; qemu_irq drq[2]; i2c_bus *bus; uint8_t revision; + void *iclk; + void *fclk; + uint8_t mask; uint16_t stat; uint16_t dma; @@ -40,12 +46,12 @@ struct omap_i2c_s { uint8_t divider; uint8_t times[2]; uint16_t test; -}; +} OMAPI2CState; #define OMAP2_INTR_REV 0x34 #define OMAP2_GC_REV 0x34 -static void omap_i2c_interrupts_update(struct omap_i2c_s *s) +static void omap_i2c_interrupts_update(OMAPI2CState *s) { qemu_set_irq(s->irq, s->stat & s->mask); if ((s->dma >> 15) & 1) /* RDMA_EN */ @@ -54,7 +60,7 @@ static void omap_i2c_interrupts_update(struct omap_i2c_s *s) qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ } -static void omap_i2c_fifo_run(struct omap_i2c_s *s) +static void omap_i2c_fifo_run(OMAPI2CState *s) { int ack = 1; @@ -122,8 +128,10 @@ static void omap_i2c_fifo_run(struct omap_i2c_s *s) s->control &= ~(1 << 1); /* STP */ } -void omap_i2c_reset(struct omap_i2c_s *s) +static void omap_i2c_reset(DeviceState *dev) { + OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, + sysbus_from_qdev(dev)); s->mask = 0; s->stat = 0; s->dma = 0; @@ -143,7 +151,7 @@ void omap_i2c_reset(struct omap_i2c_s *s) static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) { - struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; + OMAPI2CState *s = opaque; int offset = addr & OMAP_MPUI_REG_MASK; uint16_t ret; @@ -243,7 +251,7 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) static void omap_i2c_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; + OMAPI2CState *s = opaque; int offset = addr & OMAP_MPUI_REG_MASK; int nack; @@ -309,14 +317,14 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr, } if (value & 2) - omap_i2c_reset(s); + omap_i2c_reset(&s->busdev.qdev); break; case 0x24: /* I2C_CON */ s->control = value & 0xcf87; if (~value & (1 << 15)) { /* I2C_EN */ if (s->revision < OMAP2_INTR_REV) - omap_i2c_reset(s); + omap_i2c_reset(&s->busdev.qdev); break; } if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */ @@ -385,7 +393,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr, static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; + OMAPI2CState *s = opaque; int offset = addr & OMAP_MPUI_REG_MASK; switch (offset) { @@ -426,50 +434,59 @@ static const MemoryRegionOps omap_i2c_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem, - target_phys_addr_t base, - qemu_irq irq, - qemu_irq *dma, - omap_clk clk) +static int omap_i2c_init(SysBusDevice *dev) { - struct omap_i2c_s *s = (struct omap_i2c_s *) - g_malloc0(sizeof(struct omap_i2c_s)); - - /* TODO: set a value greater or equal to real hardware */ - s->revision = 0x11; - s->irq = irq; - s->drq[0] = dma[0]; - s->drq[1] = dma[1]; - s->bus = i2c_init_bus(NULL, "i2c"); - omap_i2c_reset(s); + OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, dev); - memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", 0x800); - memory_region_add_subregion(sysmem, base, &s->iomem); - - return s; + if (!s->fclk) { + hw_error("omap_i2c: fclk not connected\n"); + } + if (s->revision >= OMAP2_INTR_REV && !s->iclk) { + /* Note that OMAP1 doesn't have a separate interface clock */ + hw_error("omap_i2c: iclk not connected\n"); + } + sysbus_init_irq(dev, &s->irq); + sysbus_init_irq(dev, &s->drq[0]); + sysbus_init_irq(dev, &s->drq[1]); + memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", + (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000); + sysbus_init_mmio(dev, &s->iomem); + s->bus = i2c_init_bus(&dev->qdev, NULL); + return 0; } -struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, - qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk) -{ - struct omap_i2c_s *s = (struct omap_i2c_s *) - g_malloc0(sizeof(struct omap_i2c_s)); +static Property omap_i2c_properties[] = { + DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0), + DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk), + DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk), + DEFINE_PROP_END_OF_LIST(), +}; - s->revision = 0x34; - s->irq = irq; - s->drq[0] = dma[0]; - s->drq[1] = dma[1]; - s->bus = i2c_init_bus(NULL, "i2c"); - omap_i2c_reset(s); +static void omap_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + k->init = omap_i2c_init; + dc->props = omap_i2c_properties; + dc->reset = omap_i2c_reset; +} - memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap2.i2c", - omap_l4_region_size(ta, 0)); - omap_l4_attach(ta, 0, &s->iomem); +static TypeInfo omap_i2c_info = { + .name = "omap_i2c", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(OMAPI2CState), + .class_init = omap_i2c_class_init, +}; - return s; +static void omap_i2c_register_types(void) +{ + type_register_static(&omap_i2c_info); } -i2c_bus *omap_i2c_bus(struct omap_i2c_s *s) +i2c_bus *omap_i2c_bus(DeviceState *omap_i2c) { + OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, sysbus_from_qdev(omap_i2c)); return s->bus; } + +type_init(omap_i2c_register_types)