From patchwork Fri Feb 24 11:38:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 142815 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A36CCB6ED0 for ; Fri, 24 Feb 2012 22:38:57 +1100 (EST) Received: from localhost ([::1]:34211 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S0tUD-0005yz-JI for incoming@patchwork.ozlabs.org; Fri, 24 Feb 2012 06:38:53 -0500 Received: from eggs.gnu.org ([140.186.70.92]:43586) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S0tTy-0005gd-2X for qemu-devel@nongnu.org; Fri, 24 Feb 2012 06:38:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S0tTr-00075K-EX for qemu-devel@nongnu.org; Fri, 24 Feb 2012 06:38:36 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:43853) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S0tTq-00074K-SL for qemu-devel@nongnu.org; Fri, 24 Feb 2012 06:38:31 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1S0tTb-00077w-Sh; Fri, 24 Feb 2012 11:38:15 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 24 Feb 2012 11:38:15 +0000 Message-Id: <1330083495-27373-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Anthony Liguori , Paul Brook , patches@linaro.org Subject: [Qemu-devel] [PATCH] hw/arm11mpcore: Fix broken realview_mpcore/arm11mpcore_priv properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix confusion in the Property arrays for the "arm11mpcore_priv" (per-CPU devices for the ARM11MPcore CPU) and "realview_mpcore" (realview-eb board specific device encapsulating CPU and some extra interrupt controllers) -- the num-irq property was defined on the wrong device and the mpcore_rirq_properties were defined as offsets in the wrong structure. The effect was that the realview-eb-mpcore machine would abort on startup trying to allocate an insane amount of memory. (This bug was introduced in the QOM conversion in commit 999e12bb.) Signed-off-by: Peter Maydell --- The trouble with doing all this as macro magic is that you end up repeating yourself and nothing errors out saying "you fool, when you typed the name of the object struct for the nth time you got it wrong"... hw/arm11mpcore.c | 20 ++++++++++---------- 1 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index 102348b..c67b70f 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -202,16 +202,7 @@ static int realview_mpcore_init(SysBusDevice *dev) } static Property mpcore_rirq_properties[] = { - DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1), - /* The ARM11 MPCORE TRM says the on-chip controller may have - * anything from 0 to 224 external interrupt IRQ lines (with another - * 32 internal). We default to 32+32, which is the number provided by - * the ARM11 MPCore test chip in the Realview Versatile Express - * coretile. Other boards may differ and should set this property - * appropriately. Some Linux kernels may not boot if the hardware - * has more IRQ lines than the kernel expects. - */ - DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64), + DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -233,6 +224,15 @@ static TypeInfo mpcore_rirq_info = { static Property mpcore_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1), + /* The ARM11 MPCORE TRM says the on-chip controller may have + * anything from 0 to 224 external interrupt IRQ lines (with another + * 32 internal). We default to 32+32, which is the number provided by + * the ARM11 MPCore test chip in the Realview Versatile Express + * coretile. Other boards may differ and should set this property + * appropriately. Some Linux kernels may not boot if the hardware + * has more IRQ lines than the kernel expects. + */ + DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64), DEFINE_PROP_END_OF_LIST(), };