From patchwork Fri Feb 24 06:58:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 142757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-yw0-f56.google.com (mail-yw0-f56.google.com [209.85.213.56]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 21759B6F62 for ; Fri, 24 Feb 2012 17:41:11 +1100 (EST) Received: by yhjj63 with SMTP id j63sf15690yhj.11 for ; Thu, 23 Feb 2012 22:41:09 -0800 (PST) Received-SPF: pass (google.com: domain of rtc-linux+bncCObKqo_qFxCE4pz6BBoEVU85zA@googlegroups.com designates 10.68.199.166 as permitted sender) client-ip=10.68.199.166; Authentication-Results: mr.google.com; spf=pass (google.com: domain of rtc-linux+bncCObKqo_qFxCE4pz6BBoEVU85zA@googlegroups.com designates 10.68.199.166 as permitted sender) smtp.mail=rtc-linux+bncCObKqo_qFxCE4pz6BBoEVU85zA@googlegroups.com; dkim=pass header.i=rtc-linux+bncCObKqo_qFxCE4pz6BBoEVU85zA@googlegroups.com Received: from mr.google.com ([10.68.199.166]) by 10.68.199.166 with SMTP id jl6mr814869pbc.17.1330065669488 (num_hops = 1); Thu, 23 Feb 2012 22:41:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=beta; h=mime-version:x-beenthere:received-spf:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:x-originalarrivaltime :x-original-sender:x-original-authentication-results:reply-to :precedence:mailing-list:list-id:x-google-group-id:list-post :list-help:list-archive:sender:list-subscribe:list-unsubscribe :content-type; bh=3U2hrhUHBQvT+eelEC+6xECtF1rKdsr+S8CMybTA21w=; b=fhhECKBS1aHStnBfLeZW+tNyGAcs1u/2+8m45lxMj1OfaN0UDq29MXQEI3F9Xj0cb5 M6qeZcSJH+N+2VtO0U1v/roQKMOoorKDyJdu3wUqKQT6OBvl45VMLXNJ9gfANGccu5Kp qPwM5t7+TmEfvkYcNV2OQEW2AMb2GVNyMGIko= Received: by 10.68.199.166 with SMTP id jl6mr202067pbc.17.1330065668730; Thu, 23 Feb 2012 22:41:08 -0800 (PST) MIME-Version: 1.0 X-BeenThere: rtc-linux@googlegroups.com Received: by 10.68.118.230 with SMTP id kp6ls981042pbb.7.gmail; Thu, 23 Feb 2012 22:41:08 -0800 (PST) Received: by 10.68.213.68 with SMTP id nq4mr1283608pbc.2.1330065668454; Thu, 23 Feb 2012 22:41:08 -0800 (PST) Received: by 10.68.213.68 with SMTP id nq4mr1283607pbc.2.1330065668443; Thu, 23 Feb 2012 22:41:08 -0800 (PST) Received: from na3sys009aog108.obsmtp.com ([74.125.149.199]) by gmr-mx.google.com with SMTP id p7si4988568pbq.0.2012.02.23.22.40.46; Thu, 23 Feb 2012 22:41:08 -0800 (PST) Received-SPF: temperror (google.com: error in processing during lookup of hzhuang1@marvell.com: DNS timeout) client-ip=74.125.149.199; Received: from MSI-MTA.marvell.com ([65.219.4.132]) by na3sys009aob108.postini.com ([74.125.148.12]) with SMTP ID DSNKT0cw7ktGuWnxUgXoymu68AtcUE3XcIEy@postini.com; Thu, 23 Feb 2012 22:41:08 PST Received: from maili.marvell.com ([10.68.76.210]) by MSI-MTA.marvell.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 23 Feb 2012 22:40:45 -0800 Received: from localhost (unknown [10.38.164.65]) by maili.marvell.com (Postfix) with ESMTP id A70954E4BF; Thu, 23 Feb 2012 22:40:45 -0800 (PST) From: Haojian Zhuang To: a.zummo@towertech.it, arnd@arndb.de, rtc-linux@googlegroups.com, robert.jarzmik@free.fr, plagnioj@jcrosoft.com, linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk Cc: "Jett.Zhou" , Haojian Zhuang Subject: [rtc-linux] [PATCH v4 4/7] ARM: sa1100: clean up clock support Date: Fri, 24 Feb 2012 14:58:05 +0800 Message-Id: <1330066685-17066-1-git-send-email-haojian.zhuang@marvell.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1330012851-13693-5-git-send-email-haojian.zhuang@marvell.com> References: <1330012851-13693-5-git-send-email-haojian.zhuang@marvell.com> X-OriginalArrivalTime: 24 Feb 2012 06:40:45.0927 (UTC) FILETIME=[3CC74770:01CCF2BF] X-Original-Sender: haojian.zhuang@marvell.com X-Original-Authentication-Results: gmr-mx.google.com; spf=temperror (google.com: error in processing during lookup of hzhuang1@marvell.com: DNS timeout) smtp.mail=hzhuang1@marvell.com Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: Sender: rtc-linux@googlegroups.com List-Subscribe: , List-Unsubscribe: , From: Jett.Zhou Add rtc clock support and clean clock support for gpio. Signed-off-by: Jett.Zhou signed-off-by: Haojian Zhuang --- arch/arm/Kconfig | 2 +- arch/arm/mach-sa1100/clock.c | 82 ++++++++++++++++++++++++------------------ 2 files changed, 48 insertions(+), 36 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a48aecc..6e40039 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -754,7 +754,7 @@ config ARCH_SA1100 select ARCH_HAS_CPUFREQ select CPU_FREQ select GENERIC_CLOCKEVENTS - select HAVE_CLK + select CLKDEV_LOOKUP select HAVE_SCHED_CLOCK select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index dab3c63..172ebd0 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -11,17 +11,29 @@ #include #include #include +#include +#include #include -/* - * Very simple clock implementation - we only have one clock to deal with. - */ +struct clkops { + void (*enable)(struct clk *); + void (*disable)(struct clk *); +}; + struct clk { + const struct clkops *ops; unsigned int enabled; }; -static void clk_gpio27_enable(void) +#define DEFINE_CLK(_name, _ops) \ +struct clk clk_##_name = { \ + .ops = _ops, \ + } + +static DEFINE_SPINLOCK(clocks_lock); + +static void clk_gpio27_enable(struct clk *clk) { /* * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: @@ -32,38 +44,24 @@ static void clk_gpio27_enable(void) TUCR = TUCR_3_6864MHz; } -static void clk_gpio27_disable(void) +static void clk_gpio27_disable(struct clk *clk) { TUCR = 0; GPDR &= ~GPIO_32_768kHz; GAFR &= ~GPIO_32_768kHz; } -static struct clk clk_gpio27; - -static DEFINE_SPINLOCK(clocks_lock); - -struct clk *clk_get(struct device *dev, const char *id) -{ - const char *devname = dev_name(dev); - - return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { unsigned long flags; - spin_lock_irqsave(&clocks_lock, flags); - if (clk->enabled++ == 0) - clk_gpio27_enable(); - spin_unlock_irqrestore(&clocks_lock, flags); + if (clk) { + spin_lock_irqsave(&clocks_lock, flags); + if (clk->enabled++ == 0) + clk->ops->enable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + } + return 0; } EXPORT_SYMBOL(clk_enable); @@ -72,17 +70,31 @@ void clk_disable(struct clk *clk) { unsigned long flags; - WARN_ON(clk->enabled == 0); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->enabled == 0) - clk_gpio27_disable(); - spin_unlock_irqrestore(&clocks_lock, flags); + if (clk) { + WARN_ON(clk->enabled == 0); + spin_lock_irqsave(&clocks_lock, flags); + if (--clk->enabled == 0) + clk->ops->disable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + } } EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) +const struct clkops clk_gpio27_ops = { + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; + +static DEFINE_CLK(gpio27, &clk_gpio27_ops); + +static struct clk_lookup sa11xx_clkregs[] = { + CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), + CLKDEV_INIT("sa1100-rtc", NULL, NULL), +}; + +static int __init sa11xx_clk_init(void) { - return 3686400; + clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); + return 0; } -EXPORT_SYMBOL(clk_get_rate); +core_initcall(sa11xx_clk_init);