| Message ID | 20120224045849.GA14338@intel.com |
|---|---|
| State | New |
| Headers | show |
On Fri, Feb 24, 2012 at 5:58 AM, H.J. Lu <hongjiu.lu@intel.com> wrote: > The second form is redundant in > > ;; Stores and loads of ax to arbitrary constant address. > ;; We fake an second form of instruction to force reload to load address > ;; into register when rax is not available > (define_insn "*movabs<mode>_1" > [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) > (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))] > "TARGET_64BIT && ix86_check_movabs (insn, 0)" > "@ > movabs{<imodesuffix>}\t{%1, %P0|%P0, %1} > mov{<imodesuffix>}\t{%1, %a0|%a0, %1}" > [(set_attr "type" "imov") > (set_attr "modrm" "0,*") > (set_attr "length_address" "8,0") > (set_attr "length_immediate" "0,*") > (set_attr "memory" "store") > (set_attr "mode" "<MODE>")]) > > since it is just normal mov<mode>. Tested on Linux/x86-64. OK for stage1? I am a bit scarred by ... well ... scary comment that mentions reload. This second form predates IRA - are we sure that IRA is clever enough not to break due to this change? Jan, Vladimir, do you have any comments? Uros.
On Fri, Feb 24, 2012 at 8:11 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > On Fri, Feb 24, 2012 at 5:58 AM, H.J. Lu <hongjiu.lu@intel.com> wrote: > >> The second form is redundant in >> >> ;; Stores and loads of ax to arbitrary constant address. >> ;; We fake an second form of instruction to force reload to load address >> ;; into register when rax is not available >> (define_insn "*movabs<mode>_1" >> [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) >> (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))] >> "TARGET_64BIT && ix86_check_movabs (insn, 0)" >> "@ >> movabs{<imodesuffix>}\t{%1, %P0|%P0, %1} >> mov{<imodesuffix>}\t{%1, %a0|%a0, %1}" >> [(set_attr "type" "imov") >> (set_attr "modrm" "0,*") >> (set_attr "length_address" "8,0") >> (set_attr "length_immediate" "0,*") >> (set_attr "memory" "store") >> (set_attr "mode" "<MODE>")]) >> >> since it is just normal mov<mode>. Tested on Linux/x86-64. OK for stage1? > > I am a bit scarred by ... well ... scary comment that mentions reload. > This second form predates IRA - are we sure that IRA is clever enough > not to break due to this change? > I am afraid reload can't deal with it. I withdrew this patch.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index ec3993a..9242926 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2335,32 +2335,26 @@ (const_string "QI")))]) ;; Stores and loads of ax to arbitrary constant address. -;; We fake an second form of instruction to force reload to load address -;; into register when rax is not available (define_insn "*movabs<mode>_1" - [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) - (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))] + [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i")) + (match_operand:SWI1248x 1 "register_operand" "a"))] "TARGET_64BIT && ix86_check_movabs (insn, 0)" - "@ - movabs{<imodesuffix>}\t{%1, %P0|%P0, %1} - mov{<imodesuffix>}\t{%1, %a0|%a0, %1}" + "movabs{<imodesuffix>}\t{%1, %P0|%P0, %1}" [(set_attr "type" "imov") - (set_attr "modrm" "0,*") - (set_attr "length_address" "8,0") - (set_attr "length_immediate" "0,*") + (set_attr "modrm" "0") + (set_attr "length_address" "8") + (set_attr "length_immediate" "0") (set_attr "memory" "store") (set_attr "mode" "<MODE>")]) (define_insn "*movabs<mode>_2" - [(set (match_operand:SWI1248x 0 "register_operand" "=a,r") - (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] + [(set (match_operand:SWI1248x 0 "register_operand" "=a") + (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i")))] "TARGET_64BIT && ix86_check_movabs (insn, 1)" - "@ - movabs{<imodesuffix>}\t{%P1, %0|%0, %P1} - mov{<imodesuffix>}\t{%a1, %0|%0, %a1}" + "movabs{<imodesuffix>}\t{%P1, %0|%0, %P1}" [(set_attr "type" "imov") - (set_attr "modrm" "0,*") - (set_attr "length_address" "8,0") + (set_attr "modrm" "0") + (set_attr "length_address" "8") (set_attr "length_immediate" "0") (set_attr "memory" "load") (set_attr "mode" "<MODE>")])
Hi, The second form is redundant in ;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "*movabs<mode>_1" [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))] "TARGET_64BIT && ix86_check_movabs (insn, 0)" "@ movabs{<imodesuffix>}\t{%1, %P0|%P0, %1} mov{<imodesuffix>}\t{%1, %a0|%a0, %1}" [(set_attr "type" "imov") (set_attr "modrm" "0,*") (set_attr "length_address" "8,0") (set_attr "length_immediate" "0,*") (set_attr "memory" "store") (set_attr "mode" "<MODE>")]) since it is just normal mov<mode>. Tested on Linux/x86-64. OK for stage1? Thanks. H.J. ---- 2012-02-23 H.J. Lu <hongjiu.lu@intel.com> PR target/52352 PR target/52364 * config/i386/i386.md (*movabs<mode>_1): Remove the second form. (*movabs<mode>_2): Likewise.