From patchwork Tue Feb 21 13:57:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 142304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4B251B6EEC for ; Wed, 22 Feb 2012 00:58:25 +1100 (EST) Received: from localhost ([::1]:43332 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzqES-0006q3-LU for incoming@patchwork.ozlabs.org; Tue, 21 Feb 2012 08:58:16 -0500 Received: from eggs.gnu.org ([140.186.70.92]:48358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzqEI-0006pt-Up for qemu-devel@nongnu.org; Tue, 21 Feb 2012 08:58:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RzqE9-0004CI-Fe for qemu-devel@nongnu.org; Tue, 21 Feb 2012 08:58:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:27943) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzqE9-0004CC-74 for qemu-devel@nongnu.org; Tue, 21 Feb 2012 08:57:57 -0500 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q1LDvtYL032575 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 21 Feb 2012 08:57:55 -0500 Received: from redhat.com (vpn-200-14.tlv.redhat.com [10.35.200.14]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id q1LDvo0u014089; Tue, 21 Feb 2012 08:57:52 -0500 Date: Tue, 21 Feb 2012 15:57:58 +0200 From: "Michael S. Tsirkin" To: blauwirbel@gmail.com, agraf@suse.de, afaerber@suse.de Message-ID: <20120221135758.GA8102@redhat.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: Gerd Hoffmann , qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH] pci: set memory type for memory behind the bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org As we make upper bits in IO and prefetcheable memory registers writeable, we should declare support for 64 bit prefetcheable memory and 32 bit io in the bridge. This changes the default for apb, dec, but I'm guessing they got the defaults wrong by accident. Alternatively, we could let bridges declare lack of 64 bit support and make the upper bits read-only zero. With this applied, we can drop these bits from express code. Reported-by: Gerd Hoffmann Signed-off-by: Michael S. Tsirkin Could someone familiar with apb,dec ack this please? --- hw/pci.c | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 31d6a5f..3ca5f4c 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -611,7 +611,7 @@ static void pci_init_w1cmask(PCIDevice *dev) PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); } -static void pci_init_wmask_bridge(PCIDevice *d) +static void pci_init_mask_bridge(PCIDevice *d) { /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and PCI_SEC_LETENCY_TIMER */ @@ -632,6 +632,14 @@ static void pci_init_wmask_bridge(PCIDevice *d) /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); + /* Supported memory and i/o types */ + d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_32; + d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_32; + pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_TYPE_64); + pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_TYPE_64); + /* TODO: add this define to pci_regs.h in linux and then in qemu. */ #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ @@ -654,6 +662,9 @@ static void pci_init_wmask_bridge(PCIDevice *d) * completeness. */ pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_DISCARD_STATUS); + d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; + pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_TYPE_MASK); } static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) @@ -775,7 +786,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, pci_init_wmask(pci_dev); pci_init_w1cmask(pci_dev); if (pc->is_bridge) { - pci_init_wmask_bridge(pci_dev); + pci_init_mask_bridge(pci_dev); } if (pci_init_multifunction(bus, pci_dev)) { pci_config_free(pci_dev);