Patchwork Minor regression with kvm ioapic, gsi >= 16

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Submitter Jan Kiszka
Date Feb. 16, 2012, 8:04 p.m.
Message ID <4F3D615E.2060603@web.de>
Download mbox | patch
Permalink /patch/141674/
State New
Headers show

Comments

Jan Kiszka - Feb. 16, 2012, 8:04 p.m.
On 2012-02-16 19:55, Avi Kivity wrote:
> kvm-unit-tests.git x86/apic.flat is failing ioapic tests with
> 
> qemu-system-x86_64 -vnc :99 -device testdev,chardev=x -chardev null,id=x
> -smp 2 -kernel ./x86/apic.flat  -serial stdio
> ...
> ioapic interrupt: FAIL
> ioapic simultaneous interrupt: FAIL
> 
> This happens because the test is invoking gsi 16, which is handled by
> the non-kvm ioapic instead of the kvm ioapic.

That test should be changed anyway as the hack that allowed it so far
will break finally when we move to upstream logic. Moreover, it is
testing unused path with our current chipset. When this may change, I'm
sure we will also have better IRQ injection mechanisms by that time.

Find a patch below.

> 
> Introduced by
> 
> commit c3388c9bd8d4f4fd841b521feed20993185d9be4
> Author: Jan Kiszka <jan.kiszka@siemens.com>
> Date:   Mon Feb 6 12:20:53 2012 +0100
> 
>     qemu-kvm: Fix GSI handling with in-kernel irqchip
>    
>     Interrupt routing with in-kernel irqchip was always a mess. Now this
>     increased after latest upstream merge: we started to call ioapic_set_irq
>     also for kernel-handled interrupts.
>    
>     Reduce this mess again by using the upstream kvm_piix3_gsi_handler. It
>     is aware of the PIIX3-specific routing in KVM mode and won't call into
>     the user space APIC model (as we do not raise IRQs >= ISA_NUM_IRQS with
>     the PIIX3).
>    
>     Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
>     Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
> 
> 
> The obvious fix would be to start using upstream's kvm-ioapic, but you
> haven't, why?
> 

I did this in a separate series, see your inbox.

Jan

--------8<--------

From: Jan Kiszka <jan.kiszka@siemens.com>

Do not use unsupported IRQ numbers

The testdev is not able to trigger IRQs outside the ISA range (without
fragile hacks). But we can use lower pins as well without losing
information as the PIC is masked during the test.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 x86/apic.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

Patch

diff --git a/x86/apic.c b/x86/apic.c
index 2725b9a..9e6bff9 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -139,8 +139,8 @@  static void ioapic_isr_77(isr_regs_t *regs)
 static void test_ioapic_intr(void)
 {
     handle_irq(0x77, ioapic_isr_77);
-    set_ioapic_redir(0x10, 0x77);
-    toggle_irq_line(0x10);
+    set_ioapic_redir(0x0f, 0x77);
+    toggle_irq_line(0x0f);
     asm volatile ("nop");
     report("ioapic interrupt", g_isr_77 == 1);
 }
@@ -168,11 +168,11 @@  static void test_ioapic_simultaneous(void)
 {
     handle_irq(0x78, ioapic_isr_78);
     handle_irq(0x66, ioapic_isr_66);
-    set_ioapic_redir(0x10, 0x78);
-    set_ioapic_redir(0x11, 0x66);
+    set_ioapic_redir(0x0e, 0x78);
+    set_ioapic_redir(0x0f, 0x66);
     irq_disable();
-    toggle_irq_line(0x11);
-    toggle_irq_line(0x10);
+    toggle_irq_line(0x0e);
+    toggle_irq_line(0x0f);
     irq_enable();
     asm volatile ("nop");
     report("ioapic simultaneous interrupt",