Patchwork [U-Boot] arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer load

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Submitter Tom Warren
Date Feb. 16, 2012, 7:45 p.m.
Message ID <1329421534-12963-1-git-send-email-twarren@nvidia.com>
Download mbox | patch
Permalink /patch/141667/
State Superseded
Headers show

Comments

Tom Warren - Feb. 16, 2012, 7:45 p.m.
The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
load using a constant in tegra2_start. Break it up into 4 loads
using mov & orr.

Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/ap20.c |   25 ++++++++++++++++++++-----
 1 files changed, 20 insertions(+), 5 deletions(-)
Simon Glass - Feb. 16, 2012, 9:30 p.m.
Hi Tom,

On Feb 16, 2012 11:45 AM, "Tom Warren" <twarren.nvidia@gmail.com> wrote:
>
> The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
> load using a constant in tegra2_start. Break it up into 4 loads
> using mov & orr.
>
> Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
> compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.
>
> Signed-off-by: Tom Warren <twarren@nvidia.com>
> ---
>  arch/arm/cpu/armv7/tegra2/ap20.c |   25 ++++++++++++++++++++-----
>  1 files changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c
b/arch/arm/cpu/armv7/tegra2/ap20.c
> index 4c44bb3..d2bc0d5 100644
> --- a/arch/arm/cpu/armv7/tegra2/ap20.c
> +++ b/arch/arm/cpu/armv7/tegra2/ap20.c
> @@ -298,11 +298,26 @@ void tegra2_start(void)
>                writel(0xC0, &pmt->pmt_cfg_ctl);
>
>                /*
> -               * If we are ARM7 - give it a different stack. We are
about to
> -               * start up the A9 which will want to use this one.
> -               */
> -               asm volatile("ldr       sp, =%c0\n"
> -                       : : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
> +                * If we are ARM7 - give it a different stack. We are
about to
> +                * start up the A9 which will want to use this one.
> +                */
> +               /*
> +                * Note that the 'ldr sp,CONSTANT' version, below, doesn't
> +                * work on gcc 4.2.2 (ELDK42), but does on gcc 4.4.1 and
above.
> +                * The work-around is to use the (ugly) 4-pass mov/orr
below.
> +                *
> +                * asm volatile("ldr    sp, =%c0\n" : :
> +                *      "i"(AVP_EARLY_BOOT_STACK_LIMIT));
> +                */
> +
> +               asm volatile("mov       sp, %0"
> +                       : : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF));
> +               asm volatile("orr       sp, %0"
> +                       : : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF00));
> +               asm volatile("orr       sp, %0"
> +                       : : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF0000));
> +               asm volatile("orr       sp, %0"
> +                       : : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF000000));

Can we combine these into one asm with 4 parameters?

>
>                start_cpu((u32)_start);
>                halt_avp();
> --
> 1.7.7.1
>
Regards,
Simon
Marek Vasut - Feb. 16, 2012, 10:47 p.m.
> The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
> load using a constant in tegra2_start. Break it up into 4 loads
> using mov & orr.
> 
> Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
> compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.
> 
> Signed-off-by: Tom Warren <twarren@nvidia.com>
> ---
>  arch/arm/cpu/armv7/tegra2/ap20.c |   25 ++++++++++++++++++++-----
>  1 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c
> b/arch/arm/cpu/armv7/tegra2/ap20.c index 4c44bb3..d2bc0d5 100644
> --- a/arch/arm/cpu/armv7/tegra2/ap20.c
> +++ b/arch/arm/cpu/armv7/tegra2/ap20.c
> @@ -298,11 +298,26 @@ void tegra2_start(void)
>  		writel(0xC0, &pmt->pmt_cfg_ctl);
> 
>  		/*
> -		* If we are ARM7 - give it a different stack. We are about to
> -		* start up the A9 which will want to use this one.
> -		*/
> -		asm volatile("ldr	sp, =%c0\n"
> -			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
> +		 * If we are ARM7 - give it a different stack. We are about to
> +		 * start up the A9 which will want to use this one.
> +		 */
> +		/*
> +		 * Note that the 'ldr sp,CONSTANT' version, below, doesn't
> +		 * work on gcc 4.2.2 (ELDK42), but does on gcc 4.4.1 and above.
> +		 * The work-around is to use the (ugly) 4-pass mov/orr below.
> +		 *
> +		 * asm volatile("ldr	sp, =%c0\n" : :
> +		 *	"i"(AVP_EARLY_BOOT_STACK_LIMIT));
> +		 */
> +
> +		asm volatile("mov	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF));
> +		asm volatile("orr	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF00));
> +		asm volatile("orr	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF0000));
> +		asm volatile("orr	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF000000));

asm volatile("mov sp, %0"::"r"(AVP_EARLY_BOOT_STACK_LIMIT)); won't work?

M
> 
>  		start_cpu((u32)_start);
>  		halt_avp();
Marek Vasut - Feb. 17, 2012, 8:56 a.m.
> The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
> load using a constant in tegra2_start. Break it up into 4 loads
> using mov & orr.
> 
> Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
> compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.
> 
> Signed-off-by: Tom Warren <twarren@nvidia.com>
> ---
>  arch/arm/cpu/armv7/tegra2/ap20.c |   25 ++++++++++++++++++++-----
>  1 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c
> b/arch/arm/cpu/armv7/tegra2/ap20.c index 4c44bb3..d2bc0d5 100644
> --- a/arch/arm/cpu/armv7/tegra2/ap20.c
> +++ b/arch/arm/cpu/armv7/tegra2/ap20.c
> @@ -298,11 +298,26 @@ void tegra2_start(void)
>  		writel(0xC0, &pmt->pmt_cfg_ctl);
> 
>  		/*
> -		* If we are ARM7 - give it a different stack. We are about to
> -		* start up the A9 which will want to use this one.
> -		*/
> -		asm volatile("ldr	sp, =%c0\n"
> -			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
> +		 * If we are ARM7 - give it a different stack. We are about to
> +		 * start up the A9 which will want to use this one.
> +		 */
> +		/*
> +		 * Note that the 'ldr sp,CONSTANT' version, below, doesn't
> +		 * work on gcc 4.2.2 (ELDK42), but does on gcc 4.4.1 and above.
> +		 * The work-around is to use the (ugly) 4-pass mov/orr below.
> +		 *
> +		 * asm volatile("ldr	sp, =%c0\n" : :
> +		 *	"i"(AVP_EARLY_BOOT_STACK_LIMIT));
> +		 */
> +
> +		asm volatile("mov	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF));
> +		asm volatile("orr	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF00));
> +		asm volatile("orr	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF0000));
> +		asm volatile("orr	sp, %0"
> +			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF000000));
> 
>  		start_cpu((u32)_start);
>  		halt_avp();

I think you said you'll send an updated patch.

Patch

diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 4c44bb3..d2bc0d5 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -298,11 +298,26 @@  void tegra2_start(void)
 		writel(0xC0, &pmt->pmt_cfg_ctl);
 
 		/*
-		* If we are ARM7 - give it a different stack. We are about to
-		* start up the A9 which will want to use this one.
-		*/
-		asm volatile("ldr	sp, =%c0\n"
-			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
+		 * If we are ARM7 - give it a different stack. We are about to
+		 * start up the A9 which will want to use this one.
+		 */
+		/*
+		 * Note that the 'ldr sp,CONSTANT' version, below, doesn't
+		 * work on gcc 4.2.2 (ELDK42), but does on gcc 4.4.1 and above.
+		 * The work-around is to use the (ugly) 4-pass mov/orr below.
+		 *
+		 * asm volatile("ldr	sp, =%c0\n" : :
+		 *	"i"(AVP_EARLY_BOOT_STACK_LIMIT));
+		 */
+
+		asm volatile("mov	sp, %0"
+			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF));
+		asm volatile("orr	sp, %0"
+			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF00));
+		asm volatile("orr	sp, %0"
+			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF0000));
+		asm volatile("orr	sp, %0"
+			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT & 0xFF000000));
 
 		start_cpu((u32)_start);
 		halt_avp();