Patchwork [2/2,v2] powerpc/fsl: add PAMUBYPENR register definition to fsl_guts.h

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Submitter Timur Tabi
Date Feb. 16, 2012, 5:21 p.m.
Message ID <1329412870-16716-2-git-send-email-timur@freescale.com>
Download mbox | patch
Permalink /patch/141649/
State Deferred
Delegated to: Kumar Gala
Headers show

Comments

Timur Tabi - Feb. 16, 2012, 5:21 p.m.
Add a defintion of register PAMUBYPENR (offset 0x604) to the global
utilities structure.

PAMUBYPENR is the PAMU bypass enable register.  It contains control
bits for enabling bypass mode on each PAMU.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/include/asm/fsl_guts.h |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)
Kumar Gala - March 16, 2012, 7:07 p.m.
On Feb 16, 2012, at 11:21 AM, Timur Tabi wrote:

> Add a defintion of register PAMUBYPENR (offset 0x604) to the global
> utilities structure.
> 
> PAMUBYPENR is the PAMU bypass enable register.  It contains control
> bits for enabling bypass mode on each PAMU.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/include/asm/fsl_guts.h |    4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)

Sticking with my original point of not applying this til PAMU driver is ready as well.

- k
Timur Tabi - March 16, 2012, 7:08 p.m.
Kumar Gala wrote:
> Sticking with my original point of not applying this til PAMU driver is ready as well.

Ok.

Patch

diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index a880377..23e483d 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -69,7 +69,9 @@  struct ccsr_guts {
 	u8	res0c4[0x224 - 0xc4];
 	__be32  iodelay1;	/* 0x.0224 - IO delay control register 1 */
 	__be32  iodelay2;	/* 0x.0228 - IO delay control register 2 */
-	u8	res22c[0x800 - 0x22c];
+	u8	res22c[0x604 - 0x22c];
+	__be32	pamubypenr;	/* 0x.0604 - PAMU bypass enable register */
+	u8	res608[0x800 - 0x608];
 	__be32	clkdvdr;	/* 0x.0800 - Clock Divide Register */
 	u8	res804[0x900 - 0x804];
 	__be32	ircr;		/* 0x.0900 - Infrared Control Register */