Patchwork [libitm] : GTM_longjmp: Jump indirect from memory address

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Submitter Uros Bizjak
Date Feb. 14, 2012, 7:54 a.m.
Message ID <CAFULd4Z8BmXxHm+iBcCWfT-JKR_Z+d-p0YxkGuZ5UR77HQqkAQ@mail.gmail.com>
Download mbox | patch
Permalink /patch/141063/
State New
Headers show

Comments

Uros Bizjak - Feb. 14, 2012, 7:54 a.m.
On Tue, Feb 14, 2012 at 8:39 AM, Uros Bizjak <ubizjak@gmail.com> wrote:

>>>> - cfi_register(%rip, %rdx)
>>>> + cfi_offset(%rip, 56)
>>>
>>> Hm, we just defined new CFA as rcx+0, so we should define location of
>>> rip relative to new CFA. Since CFA points to stack slot just before
>>> return address was pushed, new rip lies at CFA-8 for 64bit resp. CFA-4
>>> for x86_32. Did I get these .cfi directives correctly?
>>
>> No.  The value at %rcx-8 is total garbage.  There no guarantee that
>> the call stack leading to this abort has anything in common with the
>> call stack that created the jmpbuf, except *above* %rcx, the new CFA.
>>
>> The new rip is at rsi+56.  You can see that in that you jump to it.
>
> Thanks for the explanation, I will commit the patch with your suggested change.

Now with the patch attached... (please also note that rip is now
defined with offset to old CFA, before CFA is updated to new
register).

Uros.
Richard Henderson - Feb. 14, 2012, 6:07 p.m.
On 02/13/2012 11:54 PM, Uros Bizjak wrote:
>  	movq	48(%rsi), %r15
> -	movq	56(%rsi), %rdx
>  	movl	%edi, %eax
> +	cfi_offset(%rip, 56)
>  	cfi_def_cfa(%rcx, 0)
> -	cfi_register(%rip, %rdx)
>  	movq	%rcx, %rsp
> -	jmp	*%rdx
> +	jmp	*56(%rsi)

I'm sorry, I was mistaken earlier.  The rip value is not at CFA+56, it's at RSI+56.
The way to describe this is

	cfi_def_cfa(%rsi, 0)
	cfi_offset(%rip, 56)
	cfi_register(%rsp, %rcx)


r~

Patch

Index: ChangeLog
===================================================================
--- ChangeLog	(revision 184197)
+++ ChangeLog	(working copy)
@@ -1,3 +1,7 @@ 
+2012-02-15  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/x86/target.h (GTM_longjmp): Jump indirect from memory address.
+
 2012-02-13  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9.
Index: config/x86/sjlj.S
===================================================================
--- config/x86/sjlj.S	(revision 184150)
+++ config/x86/sjlj.S	(working copy)
@@ -119,23 +119,21 @@ 
 	movq	32(%rsi), %r13
 	movq	40(%rsi), %r14
 	movq	48(%rsi), %r15
-	movq	56(%rsi), %rdx
 	movl	%edi, %eax
+	cfi_offset(%rip, 56)
 	cfi_def_cfa(%rcx, 0)
-	cfi_register(%rip, %rdx)
 	movq	%rcx, %rsp
-	jmp	*%rdx
+	jmp	*56(%rsi)
 #else
 	movl	(%edx), %ecx
 	movl	4(%edx), %ebx
 	movl	8(%edx), %esi
 	movl	12(%edx), %edi
 	movl	16(%edx), %ebp
-	movl	20(%edx), %edx
+	cfi_offset(%eip, 20)
 	cfi_def_cfa(%ecx, 0)
-	cfi_register(%eip, %edx)
 	movl	%ecx, %esp
-	jmp	*%edx
+	jmp	*20(%edx)
 #endif
 	cfi_endproc