From patchwork Mon Feb 13 08:57:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Bhargav X-Patchwork-Id: 140867 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 03A08B6FA8 for ; Mon, 13 Feb 2012 19:58:30 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4F83B280AB; Mon, 13 Feb 2012 09:58:29 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Tsqr3duw8c-2; Mon, 13 Feb 2012 09:58:28 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D8E428097; Mon, 13 Feb 2012 09:58:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 458AD280A2 for ; Mon, 13 Feb 2012 09:58:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id I0o-0FBPBLxg for ; Mon, 13 Feb 2012 09:58:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ahm.einfochips.com (ahm.einfochips.com [203.76.128.206]) by theia.denx.de (Postfix) with ESMTP id 9CD6428095 for ; Mon, 13 Feb 2012 09:58:21 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by ahm.einfochips.com (Postfix) with ESMTP id E85FC7FA00D2; Mon, 13 Feb 2012 14:12:27 +0530 (IST) X-Virus-Scanned: amavisd-new at einfochips.com Received: from ahm.einfochips.com ([127.0.0.1]) by localhost (ahm.einfochips.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xLxcR9XP86wQ; Mon, 13 Feb 2012 14:12:27 +0530 (IST) Received: from localhost.localdomain (unknown [10.100.4.207]) by ahm.einfochips.com (Postfix) with ESMTPA id CF8E67FA00CD; Mon, 13 Feb 2012 14:12:27 +0530 (IST) From: Ajay Bhargav To: linux@bohmer.net Date: Mon, 13 Feb 2012 14:27:24 +0530 Message-Id: <1329123447-21617-1-git-send-email-ajay.bhargav@einfochips.com> X-Mailer: git-send-email 1.7.7.2 Cc: Ajay Bhargav , u-boot@lists.denx.de Subject: [U-Boot] [v2 1/4] USB: Armada100: Add UTMI PHY interface driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds USB host controller's UTMI PHY interface driver for Armada100 SOCs. Signed-off-by: Ajay Bhargav --- Changes for v2: - Fix: enable only required clock in MPMU arch/arm/include/asm/arch-armada100/armada100.h | 8 ++ drivers/usb/host/utmi-armada100.c | 87 +++++++++++++++++++++++ drivers/usb/host/utmi-armada100.h | 79 ++++++++++++++++++++ 3 files changed, 174 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/utmi-armada100.c create mode 100644 drivers/usb/host/utmi-armada100.h diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index 0ed3a8e..70fba27 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -43,6 +43,14 @@ #define SSP2_APBCLK 0x01 #define SSP2_FNCLK 0x02 +/* USB Clock/reset control bits */ +#define USB_SPH_AXICLK_EN 0x10 +#define USB_SPH_AXI_RST 0x02 + +/* MPMU Clocks */ +#define APB2_26M_EN (1 << 20) +#define AP_26M (1 << 4) + /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_FEC_BASE 0xC0800000 diff --git a/drivers/usb/host/utmi-armada100.c b/drivers/usb/host/utmi-armada100.c new file mode 100644 index 0000000..1a4d3f2 --- /dev/null +++ b/drivers/usb/host/utmi-armada100.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2012 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "utmi-armada100.h" + +static void utmi_phy_init(void) +{ + struct armd1usb_phy_reg *phy_regs = + (struct armd1usb_phy_reg *)UTMI_PHY_BASE; + + setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); + udelay(1000); + setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); + + clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); + setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); + + setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); + + /* Calibrate pll */ + while ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0) + ; + + udelay(200); + setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); + udelay(400); + clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); + + udelay(200); + setbits_le32(&phy_regs->utmi_tx, RCAL_START); + udelay(400); + clrbits_le32(&phy_regs->utmi_tx, RCAL_START); + + while ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0) + ; +} + +/* + * Initialize USB host controller's UTMI Physical interface + */ +void utmi_init(void) +{ + struct armd1mpmu_registers *mpmu_regs = + (struct armd1mpmu_registers *)ARMD1_MPMU_BASE; + + struct armd1apmu_registers *apmu_regs = + (struct armd1apmu_registers *)ARMD1_APMU_BASE; + + /* Turn on 26Mhz ref clock for UTMI PLL */ + setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); + + /* USB Clock reset */ + writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc); + writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc); + + /* Initialize UTMI transceiver */ + utmi_phy_init(); +} diff --git a/drivers/usb/host/utmi-armada100.h b/drivers/usb/host/utmi-armada100.h new file mode 100644 index 0000000..dd0ccdb --- /dev/null +++ b/drivers/usb/host/utmi-armada100.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2012 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2009 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __UTMI_ARMADA100__ +#define __UTMI_ARMADA100__ + +#define UTMI_PHY_BASE 0xD4206000 + +/* utmi_ctrl - bits */ +#define INPKT_DELAY_SOF (1 << 28) +#define PLL_PWR_UP 2 +#define PHY_PWR_UP 1 + +/* utmi_pll - bits */ +#define PLL_FBDIV_MASK 0x00000FF0 +#define PLL_FBDIV 4 +#define PLL_REFDIV_MASK 0x0000000F +#define PLL_REFDIV 0 +#define PLL_READY 0x800000 +#define VCOCAL_START (1 << 21) + +#define N_DIVIDER 0xEE +#define M_DIVIDER 0x0B + +/* utmi_tx - bits */ +#define CK60_PHSEL 17 +#define PHSEL_VAL 0x4 +#define RCAL_START (1 << 12) + +/* + * USB PHY registers + * Refer Datasheet Appendix A.21 + */ +struct armd1usb_phy_reg { + u32 utmi_rev; /* USB PHY Revision */ + u32 utmi_ctrl; /* USB PHY Control register */ + u32 utmi_pll; /* PLL register */ + u32 utmi_tx; /* Tx register */ + u32 utmi_rx; /* Rx register */ + u32 utmi_ivref; /* IVREF register */ + u32 utmi_tst_g0; /* Test group 0 register */ + u32 utmi_tst_g1; /* Test group 1 register */ + u32 utmi_tst_g2; /* Test group 2 register */ + u32 utmi_tst_g3; /* Test group 3 register */ + u32 utmi_tst_g4; /* Test group 4 register */ + u32 utmi_tst_g5; /* Test group 5 register */ + u32 utmi_reserve; /* Reserve Register */ + u32 utmi_usb_int; /* USB interuppt register */ + u32 utmi_dbg_ctl; /* Debug control register */ + u32 utmi_otg_addon; /* OTG addon register */ +}; + +void utmi_init(void); + +#endif /* __UTMI_ARMADA100__ */