From patchwork Wed Feb 8 12:16:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Hecht X-Patchwork-Id: 140127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0233CB6F98 for ; Wed, 8 Feb 2012 23:18:49 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Rv6Sl-0001tt-C2; Wed, 08 Feb 2012 12:17:27 +0000 Received: from mail-ey0-f177.google.com ([209.85.215.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Rv6Si-0001t3-0I for linux-mtd@lists.infradead.org; Wed, 08 Feb 2012 12:17:24 +0000 Received: by eaai1 with SMTP id i1so158342eaa.36 for ; Wed, 08 Feb 2012 04:17:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=eezoJ7Xbikv7Fepi9CNSoxdhoG/AlZugSBIf5/zhKfI=; b=iG7IdDUntwxkdILW+xVUIaFbQdLLZC0TmQKv0G655rCDTLy+8wSx/vZBb+Faid0dWN qsgq6azhGrRZBn7/4Xm3sALGp1h3ZC67Thn8xPKYqi5arNcmnHZyO7g5m9iyUv9rMdYb K8bk9P2Puh5fCTSb6V0pmdpA/BTC6q7ZXfhUI= Received: by 10.213.8.3 with SMTP id f3mr2830526ebf.71.1328703440749; Wed, 08 Feb 2012 04:17:20 -0800 (PST) Received: from localhost.localdomain (i59F746F2.versanet.de. [89.247.70.242]) by mx.google.com with ESMTPS id x4sm4642273eeb.4.2012.02.08.04.17.19 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 08 Feb 2012 04:17:19 -0800 (PST) From: Bastian Hecht To: linux-mtd@lists.infradead.org, linux-sh@vger.kernel.org Subject: [PATCH 1/7] mtd: sh_flctl: Update FLCMNCR register bit field Date: Wed, 8 Feb 2012 13:16:45 +0100 Message-Id: <1328703411-3452-1-git-send-email-hechtb@gmail.com> X-Mailer: git-send-email 1.7.5.4 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (hechtb[at]googlemail.com) -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.177 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Bastian Hecht , magnus.damm@gmail.com, laurent.pinchart@ideasonboard.com X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Updates the FLCMNCR bit field to match the newest hardware generation. Some defines are added to select an appropriate clocking scheme. Signed-off-by: Bastian Hecht --- include/linux/mtd/sh_flctl.h | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-) diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h index 9cf4c4c..ecbf3e6 100644 --- a/include/linux/mtd/sh_flctl.h +++ b/include/linux/mtd/sh_flctl.h @@ -67,6 +67,30 @@ #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ #define TYPESEL_SET (0x1 << 0) +/* + * Clock settings using the PULSEx registers from FLCMNCR + * + * Some hardware uses registers called PULSEx instead of FCKSEL_E and QTSEL_E + * to control the clock divider used between the High-Speed Peripheral Clock + * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit + * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16 + * bit version the divider is seperate for the pulse width of high and low + * signals. + */ +#define PULSE3 (0x1 << 27) +#define PULSE2 (0x1 << 17) +#define PULSE1 (0x1 << 15) +#define PULSE0 (0x1 << 9) +#define CLK_8_BIT_0_5HP PULSE1 +#define CLK_8_BIT_1HP 0x0 +#define CLK_8_BIT_1_5HP (PULSE1 | PULSE2) +#define CLK_8_BIT_2HP PULSE0 +#define CLK_8_BIT_3HP (PULSE0 | PULSE1 | PULSE2) +#define CLK_8_BIT_4HP (PULSE0 | PULSE2) +#define CLK_16_BIT_6HP_LOW_2HP_HIGH PULSE0 +#define CLK_16_BIT_9HP_LOW_3HP_HIGH (PULSE0 | PULSE1 | PULSE2) +#define CLK_16_BIT_12HP_LOW_4HP_HIGH (PULSE0 | PULSE2) + /* FLCMDCR control bits */ #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ #define ADRMD_E (0x1 << 26) /* Sector address access */